Revert "[iot] Decrease panbell DDR frequency to 1600 MTS"
- temp fix for boot hangup with camera This reverts commit a8109598e7dca72d415ad5d26ac5868b88da9dfc. Bug: 115532706 Test: test boot up Change-Id: I7bb1bc14eb81ae0965fc03abdf5cb65444720d13
This commit is contained in:
Keun-young Park
faqiang.zhu
parent
b57739cac7
commit
40e0de680b
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@ -26,9 +26,143 @@
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#endif
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#define SILICON_TRAIN
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volatile unsigned int tmp, tmp_t, i;
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void lpddr4_800MHz_cfg_umctl2(void)
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{
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000);
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/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
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/* bank interleave */
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001);
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/* performance setting */
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dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
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dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
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dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
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dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
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dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
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dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
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dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
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dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
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dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
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dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
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dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
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dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
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}
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void lpddr4_100MHz_cfg_umctl2(void)
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{
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reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
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reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
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reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
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reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
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reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
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reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
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reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
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reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
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reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
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reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
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reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
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reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
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reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
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reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
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reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
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reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
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reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
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reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
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reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
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reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
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reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
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}
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void lpddr4_25MHz_cfg_umctl2(void)
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{
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reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
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reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
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reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
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reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
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reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
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reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
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reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
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reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
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reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
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reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
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reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
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reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
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reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
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reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
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reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
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reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
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reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
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reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
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reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
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reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
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reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
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}
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int get_imx8m_baseboard_id(void);
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void ddr_cfg_phy(void);
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volatile unsigned int tmp, tmp_t, i;
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void ddr_init(void)
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{
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int board_id = 0;
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@ -45,7 +179,7 @@ void ddr_init(void)
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reg32_write(0x303a00f8,tmp);
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reg32_write(0x30391000,0x8f000000);
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reg32_write(0x30391004,0x8f000000);
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reg32_write(0x30360068,0xac0784);
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reg32_write(0x30360068,0xece580);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x80;
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reg32_write(0x30360060,tmp);
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@ -67,40 +201,40 @@ void ddr_init(void)
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reg32_write(0x3d400030,0x1);
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reg32_write(0x3d400000,0xa1080020);
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reg32_write(0x3d400028,0x0);
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reg32_write(0x3d400020,0x101);
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reg32_write(0x3d400024,0xc35000);
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reg32_write(0x3d400064,0x300048);
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reg32_write(0x3d4000d0,0xc002030f);
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reg32_write(0x3d4000d4,0x500000);
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reg32_write(0x3d4000dc,0xa40012);
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reg32_write(0x3d400020,0x203);
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reg32_write(0x3d400024,0x186a000);
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reg32_write(0x3d400064,0x610090);
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reg32_write(0x3d4000d0,0xc003061c);
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reg32_write(0x3d4000d4,0x9e0000);
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reg32_write(0x3d4000dc,0xd4002d);
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reg32_write(0x3d4000e0,0x310008);
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reg32_write(0x3d4000e8,0x66004a);
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reg32_write(0x3d4000ec,0x16004a);
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reg32_write(0x3d400100,0x10100d11);
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reg32_write(0x3d400104,0x3041a);
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reg32_write(0x3d40010c,0x606000);
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reg32_write(0x3d400110,0x8040408);
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reg32_write(0x3d400114,0x2030606);
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reg32_write(0x3d400118,0x1010004);
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reg32_write(0x3d40011c,0x301);
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reg32_write(0x3d400130,0x20300);
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reg32_write(0x3d400134,0xa100002);
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reg32_write(0x3d400138,0x4b);
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reg32_write(0x3d400144,0x500028);
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reg32_write(0x3d400180,0x190000c);
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reg32_write(0x3d400184,0x14030d4);
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reg32_write(0x3d400100,0x1a201b22);
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reg32_write(0x3d400104,0x60633);
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reg32_write(0x3d40010c,0xc0c000);
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reg32_write(0x3d400110,0xf04080f);
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reg32_write(0x3d400114,0x2040c0c);
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reg32_write(0x3d400118,0x1010007);
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reg32_write(0x3d40011c,0x401);
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reg32_write(0x3d400130,0x20600);
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reg32_write(0x3d400134,0xc100002);
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reg32_write(0x3d400138,0x96);
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reg32_write(0x3d400144,0xa00050);
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reg32_write(0x3d400180,0x3200018);
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reg32_write(0x3d400184,0x28061a8);
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reg32_write(0x3d400188,0x0);
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reg32_write(0x3d400190,0x4898204);
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reg32_write(0x3d400190,0x497820a);
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reg32_write(0x3d400194,0x80303);
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reg32_write(0x3d4001a0,0xe0400018);
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reg32_write(0x3d4001a4,0xdf00e4);
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reg32_write(0x3d4001a8,0x80000000);
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reg32_write(0x3d4001b0,0x11);
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reg32_write(0x3d4001b4,0x904);
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reg32_write(0x3d4001b4,0x170a);
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reg32_write(0x3d4001c0,0x1);
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reg32_write(0x3d4001c4,0x1);
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reg32_write(0x3d4000f4,0x639);
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reg32_write(0x3d400108,0x4070b0d);
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reg32_write(0x3d400108,0x70e1214);
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reg32_write(0x3d400200,0x1f);
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reg32_write(0x3d40020c,0x0);
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reg32_write(0x3d400210,0x1f1f);
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@ -242,159 +376,40 @@ void ddr_init(void)
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/* enable port 0 */
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reg32_write(DDRC_PCTRL_0(0), 0x00000001);
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tmp = reg32_read(DDRC_CRCPARSTAT(0));
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reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
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/* enable DDR auto-refresh mode */
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tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
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reg32_write(DDRC_RFSHCTL3(0), tmp);
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} else {
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/** Initialize DDR clock and DDRC registers **/
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reg32_write(0x3038a088,0x7070000);
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reg32_write(0x3038a084,0x4030000);
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reg32_write(0x303a00ec,0xffff);
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tmp=reg32_read(0x303a00f8);
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tmp |= 0x20;
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reg32_write(0x303a00f8,tmp);
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reg32_write(0x30391000,0x8f000000);
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reg32_write(0x30391004,0x8f000000);
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reg32_write(0x30360068,0xbbe582);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x80;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp |= 0x200;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x20;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x10;
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reg32_write(0x30360060,tmp);
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do{
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tmp=reg32_read(0x30360060);
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if(tmp&0x80000000) break;
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}while(1);
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reg32_write(0x30391000,0x8f000006);
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reg32_write(0x3d400304,0x1);
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reg32_write(0x3d400030,0x1);
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reg32_write(0x3d400000,0x83080020);
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reg32_write(0x3d400064,0x300070);
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reg32_write(0x3d4000d0,0xc002030e);
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reg32_write(0x3d4000d4,0x4f0000);
|
||||
reg32_write(0x3d4000dc,0xa40012);
|
||||
reg32_write(0x3d4000e0,0x310008);
|
||||
reg32_write(0x3d4000e8,0x46004d);
|
||||
reg32_write(0x3d4000ec,0x15004d);
|
||||
reg32_write(0x3d4000f4,0x639);
|
||||
reg32_write(0x3d400100,0x10100d11);
|
||||
reg32_write(0x3d400104,0x3031a);
|
||||
reg32_write(0x3d400108,0x4070a0d);
|
||||
reg32_write(0x3d40010c,0x606000);
|
||||
reg32_write(0x3d400110,0x8040408);
|
||||
reg32_write(0x3d400114,0x2030606);
|
||||
reg32_write(0x3d400118,0x1010004);
|
||||
reg32_write(0x3d40011c,0x301);
|
||||
reg32_write(0x3d400130,0x20300);
|
||||
reg32_write(0x3d400134,0xb100002);
|
||||
reg32_write(0x3d400138,0x73);
|
||||
reg32_write(0x3d400144,0x500028);
|
||||
reg32_write(0x3d400180,0x190000c);
|
||||
reg32_write(0x3d400184,0x14030d4);
|
||||
reg32_write(0x3d400190,0x4898204);
|
||||
reg32_write(0x3d400194,0x80303);
|
||||
reg32_write(0x3d4001b4,0x904);
|
||||
reg32_write(0x3d4001b0,0x11);
|
||||
reg32_write(0x3d4001a0,0xe0400018);
|
||||
reg32_write(0x3d4001a4,0xdf00e4);
|
||||
reg32_write(0x3d4001a8,0x0);
|
||||
reg32_write(0x3d4001c0,0x1);
|
||||
reg32_write(0x3d4001c4,0x1);
|
||||
reg32_write(0x3d400200,0x15);
|
||||
reg32_write(0x3d40020c,0x0);
|
||||
reg32_write(0x3d400210,0x1f1f);
|
||||
reg32_write(0x3d400204,0x80808);
|
||||
reg32_write(0x3d400214,0x7070707);
|
||||
reg32_write(0x3d400218,0x48080707);
|
||||
reg32_write(0x3d400244,0x0);
|
||||
reg32_write(0x3d40025c,0x9);
|
||||
reg32_write(0x3d400490,0x1);
|
||||
reg32_write(0x30391000,0x8f000004);
|
||||
reg32_write(0x30391000,0x8f000000);
|
||||
reg32_write(0x3d400304,0x0);
|
||||
reg32_write(0x3d400030,0xa8);
|
||||
reg32_write(0x3d400320,0x0);
|
||||
reg32_write(0x3d000000,0x1);
|
||||
reg32_write(0x3d4001b0,0x10);
|
||||
reg32_write(0x3d402100,0xa040305);
|
||||
reg32_write(0x3d402104,0x30407);
|
||||
reg32_write(0x3d402108,0x203060b);
|
||||
reg32_write(0x3d40210c,0x505000);
|
||||
reg32_write(0x3d402110,0x2040202);
|
||||
reg32_write(0x3d402114,0x2030202);
|
||||
reg32_write(0x3d402118,0x1010004);
|
||||
reg32_write(0x3d40211c,0x301);
|
||||
reg32_write(0x3d402138,0x1d);
|
||||
reg32_write(0x3d402144,0x14000a);
|
||||
reg32_write(0x3d403024,0x30d400);
|
||||
reg32_write(0x3d402050,0x20d040);
|
||||
reg32_write(0x3d402190,0x3818200);
|
||||
reg32_write(0x3d4021b4,0x100);
|
||||
reg32_write(0x3d402064,0xc001c);
|
||||
reg32_write(0x3d4020dc,0x840000);
|
||||
reg32_write(0x3d4020e8,0x46004d);
|
||||
reg32_write(0x3d4020ec,0x15004d);
|
||||
reg32_write(0x3d4020e0,0x310000);
|
||||
reg32_write(0x3d403100,0x6010102);
|
||||
reg32_write(0x3d403104,0x30404);
|
||||
reg32_write(0x3d403108,0x203060b);
|
||||
reg32_write(0x3d40310c,0x505000);
|
||||
reg32_write(0x3d403110,0x2040202);
|
||||
reg32_write(0x3d403114,0x2030202);
|
||||
reg32_write(0x3d403118,0x1010004);
|
||||
reg32_write(0x3d40311c,0x301);
|
||||
reg32_write(0x3d403138,0x8);
|
||||
reg32_write(0x3d403144,0x50003);
|
||||
reg32_write(0x3d403024,0xc3500);
|
||||
reg32_write(0x3d403050,0x20d040);
|
||||
reg32_write(0x3d403190,0x3818200);
|
||||
reg32_write(0x3d4031b4,0x100);
|
||||
reg32_write(0x3d403064,0x30007);
|
||||
reg32_write(0x3d4030dc,0x840000);
|
||||
reg32_write(0x3d4030e8,0x46004d);
|
||||
reg32_write(0x3d4030ec,0x15004d);
|
||||
reg32_write(0x3d4030e0,0x310000);
|
||||
reg32_write(0x3c040280,0x0);
|
||||
reg32_write(0x3c040284,0x1);
|
||||
reg32_write(0x3c040288,0x2);
|
||||
reg32_write(0x3c04028c,0x3);
|
||||
reg32_write(0x3c040290,0x4);
|
||||
reg32_write(0x3c040294,0x5);
|
||||
reg32_write(0x3c040298,0x6);
|
||||
reg32_write(0x3c04029c,0x7);
|
||||
reg32_write(0x3c044280,0x0);
|
||||
reg32_write(0x3c044284,0x1);
|
||||
reg32_write(0x3c044288,0x2);
|
||||
reg32_write(0x3c04428c,0x3);
|
||||
reg32_write(0x3c044290,0x4);
|
||||
reg32_write(0x3c044294,0x5);
|
||||
reg32_write(0x3c044298,0x6);
|
||||
reg32_write(0x3c04429c,0x7);
|
||||
reg32_write(0x3c048280,0x0);
|
||||
reg32_write(0x3c048284,0x1);
|
||||
reg32_write(0x3c048288,0x2);
|
||||
reg32_write(0x3c04828c,0x3);
|
||||
reg32_write(0x3c048290,0x4);
|
||||
reg32_write(0x3c048294,0x5);
|
||||
reg32_write(0x3c048298,0x6);
|
||||
reg32_write(0x3c04829c,0x7);
|
||||
reg32_write(0x3c04c280,0x0);
|
||||
reg32_write(0x3c04c284,0x1);
|
||||
reg32_write(0x3c04c288,0x2);
|
||||
reg32_write(0x3c04c28c,0x3);
|
||||
reg32_write(0x3c04c290,0x4);
|
||||
reg32_write(0x3c04c294,0x5);
|
||||
reg32_write(0x3c04c298,0x6);
|
||||
reg32_write(0x3c04c29c,0x7);
|
||||
/* Default use 3G DDR */
|
||||
/* change the clock source of dram_apb_clk_root */
|
||||
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
|
||||
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
|
||||
|
||||
/* disable the clock gating */
|
||||
reg32_write(0x303A00EC,0x0000ffff);
|
||||
reg32setbit(0x303A00F8,5);
|
||||
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
|
||||
|
||||
dram_pll_init(SSCG_PLL_OUT_800M);
|
||||
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
|
||||
|
||||
/* Configure uMCTL2's registers */
|
||||
lpddr4_800MHz_cfg_umctl2();
|
||||
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
|
||||
|
||||
reg32_write(DDRC_DBG1(0), 0x00000000);
|
||||
tmp = reg32_read(DDRC_PWRCTL(0));
|
||||
reg32_write(DDRC_PWRCTL(0), 0x000000a8);
|
||||
/* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
|
||||
reg32_write(DDRC_SWCTL(0), 0x00000000);
|
||||
reg32_write(DDRC_DDR_SS_GPR0, 0x01);
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000010);
|
||||
|
||||
/* Configure LPDDR4 PHY's registers */
|
||||
ddr_cfg_phy();
|
||||
lpddr4_800M_cfg_phy();
|
||||
|
||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
||||
reg32_write(DDRC_SWCTL(0), 0x0000);
|
||||
|
|
@ -444,5 +459,16 @@ void ddr_init(void)
|
|||
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0);
|
||||
lpddr4_100MHz_cfg_umctl2();
|
||||
lpddr4_25MHz_cfg_umctl2();
|
||||
reg32_write(DDRC_SWCTL(0), 0x1);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
|
||||
;
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue