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mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT 

This should make it clear that this symbol is meant to be defined by
board headers.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Phil Sutter 2015-12-25 14:41:23 +01:00 committed by Stefan Roese
parent 4290252148
commit 4444d230ac
2 changed files with 11 additions and 11 deletions
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2
drivers/ddr/marvell/axp/ddr3_axp_config.h
View File

@ -51,7 +51,7 @@
#define DRAM_ECC 0 #define DRAM_ECC 0
#endif #endif
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
#define BUS_WIDTH 32 #define BUS_WIDTH 32
#else #else
#define BUS_WIDTH 64 #define BUS_WIDTH 64

20
drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
View File

@ -8,9 +8,9 @@
#define __AXP_MC_STATIC_H #define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
#else /*MV_DDR_64BIT */ #else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif #endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */ {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
}; };
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
#else /*MV_DDR_64BIT */ #else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif #endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */ {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
}; };
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
#else /* MV_DDR_64BIT */ #else /* CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
#endif #endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */ {0x00001404, 0x3630B840}, /*Dunit Control Low Register */
@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
}; };
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
#else /*MV_DDR_64BIT */ #else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif #endif
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */ {0x00001404, 0x3630B040}, /*Dunit Control Low Register */
@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
}; };
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef MV_DDR_32BIT #ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
#else /*MV_DDR_64BIT */ #else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
#endif #endif