armv7: adapt omap3 to the new cache maintenance framework
adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
This commit is contained in:
Aneesh V
Albert ARIBAUD
parent
8b457fa828
commit
45bf05854b
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@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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SOBJS += cache.o
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COBJS += board.o
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COBJS += clock.o
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@ -37,8 +37,12 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/cache.h>
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#include <asm/armv7.h>
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/* Declarations */
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extern omap3_sysinfo sysinfo;
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static void omap3_setup_aux_cr(void);
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static void omap3_invalidate_l2_cache_secure(void);
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/******************************************************************************
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* Routine: delay
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@ -166,27 +170,13 @@ void s_init(void)
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try_unlock_memory();
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/*
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* Right now flushing at low MPU speed.
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* Need to move after clock init
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*/
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invalidate_dcache(get_device_type());
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#ifndef CONFIG_ICACHE_OFF
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icache_enable();
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#endif
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/* Errata workarounds */
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omap3_setup_aux_cr();
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#ifdef CONFIG_L2_OFF
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l2_cache_disable();
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#else
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l2_cache_enable();
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/* Invalidate L2-cache from secure mode */
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omap3_invalidate_l2_cache_secure();
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#endif
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/*
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* Writing to AuxCR in U-boot using SMI for GP DEV
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* Currently SMI in Kernel on ES2 devices seems to have an issue
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* Once that is resolved, we can postpone this config to kernel
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*/
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if (get_device_type() == GP_DEVICE)
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setup_auxcr();
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set_muxconf_regs();
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delay(100);
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@ -292,3 +282,111 @@ int checkboard (void)
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
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{
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u32 i, num_params = *parameters;
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u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
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/*
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* copy the parameters to an un-cached area to avoid coherency
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* issues
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*/
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for (i = 0; i < num_params; i++) {
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__raw_writel(*parameters, sram_scratch_space);
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parameters++;
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sram_scratch_space++;
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}
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/* Now make the PPA call */
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do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
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}
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static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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if (get_device_type() == GP_DEVICE) {
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omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
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acr);
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} else {
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struct emu_hal_params emu_romcode_params;
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emu_romcode_params.num_params = 1;
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emu_romcode_params.param1 = acr;
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omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
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(u32 *)&emu_romcode_params);
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}
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}
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static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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/* Write ACR - affects non-secure banked bits */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
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}
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static void omap3_setup_aux_cr(void)
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{
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/* Workaround for Cortex-A8 errata: #454179 #430973
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* Set "IBE" bit
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* Set "Disable Brach Size Mispredicts" bit
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* Workaround for erratum #621766
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* Enable L1NEON bit
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* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
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*/
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omap3_update_aux_cr_secure(0xE0, 0);
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}
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/* Invalidate the entire L2 cache from secure mode */
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static void omap3_invalidate_l2_cache_secure(void)
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{
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if (get_device_type() == GP_DEVICE) {
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omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
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0);
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} else {
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struct emu_hal_params emu_romcode_params;
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emu_romcode_params.num_params = 1;
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emu_romcode_params.param1 = 0;
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omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
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(u32 *)&emu_romcode_params);
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}
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}
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void v7_outer_cache_enable(void)
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{
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/* Set L2EN */
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omap3_update_aux_cr_secure(0x2, 0);
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/*
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* On some revisions L2EN bit is banked on some revisions it's not
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* No harm in setting both banked bits(in fact this is required
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* by an erratum)
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*/
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omap3_update_aux_cr(0x2, 0);
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}
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void v7_outer_cache_disable(void)
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{
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/* Clear L2EN */
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omap3_update_aux_cr_secure(0, 0x2);
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/*
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* On some revisions L2EN bit is banked on some revisions it's not
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* No harm in clearing both banked bits(in fact this is required
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* by an erratum)
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*/
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omap3_update_aux_cr(0, 0x2);
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}
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#endif
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@ -1,263 +0,0 @@
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/*
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* Copyright (c) 2009 Wind River Systems, Inc.
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* Tom Rix <Tom.Rix@windriver.com>
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*
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* This file is based on and replaces the existing cache.c file
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* The copyrights for the cache.c file are:
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*
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* (C) Copyright 2008 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/omap3.h>
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/*
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* omap3 cache code
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*/
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.align 5
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.global invalidate_dcache
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.global l2_cache_enable
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.global l2_cache_disable
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.global setup_auxcr
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/*
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* invalidate_dcache()
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*
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* Invalidate the whole D-cache.
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*
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* Corrupted registers: r0-r5, r7, r9-r11
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*
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* - mm - mm_struct describing address space
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*/
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invalidate_dcache:
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stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
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mov r7, r0 @ take a backup of device type
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cmp r0, #0x3 @ check if the device type is
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@ GP
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moveq r12, #0x1 @ set up to invalide L2
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smi: .word 0x01600070 @ Call SMI monitor (smieq)
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cmp r7, #0x3 @ compare again in case its
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@ lost
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beq finished_inval @ if GP device, inval done
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@ above
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished_inval @ if loc is 0, then no need to
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@ clean
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mov r10, #0 @ start clean at cache level 0
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inval_loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache
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@ level
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mov r1, r0, lsr r2 @ extract cache type bits from
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@ clidr
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and r1, r1, #7 @ mask of the bits for current
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@ cache only
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cmp r1, #2 @ see what cache we have at
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@ this level
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blt skip_inval @ skip if no cache, or just
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@ i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mov r2, #0 @ operand for mcr SBZ
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mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
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@ sych the new cssr&csidr,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the
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@ cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the
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@ way size
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clz r5, r4 @ find bit position of way
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@ size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the
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@ index size
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inval_loop2:
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mov r9, r4 @ create working copy of max
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@ way size
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inval_loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number
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@ into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge inval_loop3
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subs r7, r7, #1 @ decrement the index
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bge inval_loop2
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skip_inval:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt inval_loop1
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finished_inval:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
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l2_cache_set:
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stmfd r13!, {r4 - r6, lr}
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mov r5, r0
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bl get_cpu_rev
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mov r4, r0
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bl get_cpu_family
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@ ES2 onwards we can disable/enable L2 ourselves
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cmp r0, #CPU_OMAP34XX
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cmpeq r4, #CPU_3XX_ES10
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mrc 15, 0, r0, cr1, cr0, 1
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bic r0, r0, #2
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orr r0, r0, r5, lsl #1
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mcreq 15, 0, r0, cr1, cr0, 1
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@ GP Device ROM code API usage here
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@ r12 = AUXCR Write function and r0 value
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mov ip, #3
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@ SMCNE instruction to call ROM Code API
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.word 0x11600070
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ldmfd r13!, {r4 - r6, pc}
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l2_cache_enable:
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mov r0, #1
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b l2_cache_set
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l2_cache_disable:
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mov r0, #0
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b l2_cache_set
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/******************************************************************************
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* Routine: setup_auxcr()
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* Description: Write to AuxCR desired value using SMI.
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* general use.
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*****************************************************************************/
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setup_auxcr:
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r2, r0, #0x00f00000 @ variant
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and r3, r0, #0x0000000f @ revision
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orr r1, r3, r2, lsr #20-4 @ combine variant and revision
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mov r12, #0x3
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x10 @ Enable ASA
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@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
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cmp r1, #0x21
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orrlt r0, r0, #1 << 5
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.word 0xE1600070 @ SMC
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mov r12, #0x2
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mrc p15, 1, r0, c9, c0, 2
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@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
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cmp r1, #0x21
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orrlt r0, r0, #1 << 27
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.word 0xE1600070 @ SMC
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bx lr
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.align 5
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.global v7_flush_dcache_all
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.global v7_flush_cache_all
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* - mm - mm_struct describing address space
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*/
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v7_flush_dcache_all:
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# dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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# dsb
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mov pc, lr
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/*
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* v7_flush_cache_all()
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*
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* Flush the entire cache system.
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* The data cache flush is now achieved using atomic clean / invalidates
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* working outwards from L1 cache. This is done using Set/Way based cache
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* maintainance instructions.
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* The instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*
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*/
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v7_flush_cache_all:
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stmfd sp!, {r0-r7, r9-r11, lr}
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bl v7_flush_dcache_all
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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ldmfd sp!, {r0-r7, r9-r11, lr}
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mov pc, lr
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@ -35,6 +35,38 @@
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
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.global omap3_gp_romcode_call
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omap3_gp_romcode_call:
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PUSH {r4-r12, lr} @ Save all registers from ROM code!
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MOV r12, r0 @ Copy the Service ID in R12
|
||||
MOV r0, r1 @ Copy parameter to R0
|
||||
mcr p15, 0, r0, c7, c10, 4 @ DSB
|
||||
mcr p15, 0, r0, c7, c10, 5 @ DMB
|
||||
.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
|
||||
@ because we use -march=armv5
|
||||
POP {r4-r12, pc}
|
||||
|
||||
/*
|
||||
* Funtion for making PPA HAL API calls in secure devices
|
||||
* Input:
|
||||
* R0 - Service ID
|
||||
* R1 - paramer list
|
||||
*/
|
||||
.global do_omap3_emu_romcode_call
|
||||
do_omap3_emu_romcode_call:
|
||||
PUSH {r4-r12, lr} @ Save all registers from ROM code!
|
||||
MOV r12, r0 @ Copy the Secure Service ID in R12
|
||||
MOV r3, r1 @ Copy the pointer to va_list in R3
|
||||
MOV r1, #0 @ Process ID - 0
|
||||
MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
|
||||
@ to va_list in R3
|
||||
MOV r6, #0xFF @ Indicate new Task call
|
||||
mcr p15, 0, r0, c7, c10, 4 @ DSB
|
||||
mcr p15, 0, r0, c7, c10, 5 @ DMB
|
||||
.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
|
||||
@ because we use -march=armv5
|
||||
POP {r4-r12, pc}
|
||||
|
||||
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
|
||||
/**************************************************************************
|
||||
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
|
||||
|
|
|
|||
|
|
@ -159,8 +159,14 @@ struct gpio {
|
|||
#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
|
||||
SRAM_OFFSET2)
|
||||
|
||||
#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */
|
||||
#define OMAP3_PUBLIC_SRAM_END 0x40210000
|
||||
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
|
||||
|
||||
/* scratch area - accessible on both EMU and GP */
|
||||
#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE
|
||||
|
||||
#define DEBUG_LED1 149 /* gpio */
|
||||
#define DEBUG_LED2 150 /* gpio */
|
||||
|
||||
|
|
@ -227,4 +233,18 @@ struct gpio {
|
|||
|
||||
#define OMAP3730 0x0c00
|
||||
|
||||
/*
|
||||
* ROM code API related flags
|
||||
*/
|
||||
#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
|
||||
#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
|
||||
|
||||
/*
|
||||
* EMU device PPA HAL related flags
|
||||
*/
|
||||
#define OMAP3_EMU_HAL_API_L2_INVAL 40
|
||||
#define OMAP3_EMU_HAL_API_WRITE_ACR 42
|
||||
|
||||
#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,11 @@ typedef struct {
|
|||
char *nand_string;
|
||||
} omap3_sysinfo;
|
||||
|
||||
struct emu_hal_params {
|
||||
u32 num_params;
|
||||
u32 param1;
|
||||
};
|
||||
|
||||
void prcm_init(void);
|
||||
void per_clocks_enable(void);
|
||||
|
||||
|
|
@ -53,9 +58,7 @@ u32 is_running_in_sdram(void);
|
|||
u32 is_running_in_sram(void);
|
||||
u32 is_running_in_flash(void);
|
||||
u32 get_device_type(void);
|
||||
void l2cache_enable(void);
|
||||
void secureworld_exit(void);
|
||||
void setup_auxcr(void);
|
||||
void try_unlock_memory(void);
|
||||
u32 get_boot_type(void);
|
||||
void invalidate_dcache(u32);
|
||||
|
|
@ -66,5 +69,6 @@ void make_cs1_contiguous(void);
|
|||
void omap_nand_switch_ecc(int);
|
||||
void power_init_r(void);
|
||||
void dieid_num_r(void);
|
||||
|
||||
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
|
||||
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue