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ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900 

The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn
DRAM controller registers so the DRAM module will be correctly
recognised.

Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Christoph G. Baumann 2013-10-28 12:29:31 +01:00 committed by Stefano Babic
parent a0f9761075
commit 465ac5891c
1 changed files with 13 additions and 0 deletions
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13
board/ppcag/bg0900/spl_boot.c
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@ -118,6 +118,19 @@ const iomux_cfg_t iomux_setup[] = {
void mxs_adjust_memory_params(uint32_t *dram_vals) void mxs_adjust_memory_params(uint32_t *dram_vals)
{ {
/*
* DDR Controller Registers
* Manufacturer: Winbond
* Device Part Number: W972GG6JB-25I
* Clock Freq.: 200MHz
* Density: 2Gb
* Chip Selects: 1
* Number of Banks: 8
* Row address: 14
* Column address: 10
*/
dram_vals[0x74 / 4] = 0x0102010A;
dram_vals[0x98 / 4] = 0x04005003; dram_vals[0x98 / 4] = 0x04005003;
dram_vals[0x9c / 4] = 0x090000c8; dram_vals[0x9c / 4] = 0x090000c8;