ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
All these files comes from kernel v4.15-rc1. Update some header with correct STMicroelectronics Copyright. Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
Tom Rini
parent
d852600ef0
commit
46b1e54b18
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@ -213,6 +213,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb
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dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
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dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
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stm32f769-disco.dtb
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stm32f769-disco.dtb
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dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
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dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
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@ -0,0 +1,344 @@
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
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st,bank-name = "GPIOK";
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};
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart3_pins_a: usart3@0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
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bias-disable;
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};
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};
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usbotg_fs_pins_a: usbotg_fs@0 {
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pins {
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pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
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<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
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<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_fs_pins_b: usbotg_fs@1 {
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pins {
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pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
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<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
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<STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_hs_pins_a: usbotg_hs@0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
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<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
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<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
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<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
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<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
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<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
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<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
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<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
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<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
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<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
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<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
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<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
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<STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
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<STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
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<STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
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<STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
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<STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
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<STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
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slew-rate = <2>;
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};
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};
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adc3_in8_pin: adc@200 {
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pins {
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pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
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};
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};
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pwm1_pins: pwm@1 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
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<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
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<STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
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};
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};
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pwm3_pins: pwm@3 {
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pins {
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pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
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<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
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};
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};
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i2c1_pins: i2c1@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
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<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
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bias-disable;
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drive-open-drain;
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slew-rate = <3>;
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};
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};
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
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<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
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<STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
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<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
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<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
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<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
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<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
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<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
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<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
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<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
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<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
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<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
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<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
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<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
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<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
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<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
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<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
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<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
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<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
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<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
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<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
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<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
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<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
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<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
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<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
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<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
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<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
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<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
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slew-rate = <2>;
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};
|
||||||
|
};
|
||||||
|
|
||||||
|
dcmi_pins: dcmi@0 {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
|
||||||
|
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
|
||||||
|
<STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
|
||||||
|
<STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
|
||||||
|
<STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
|
||||||
|
<STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
|
||||||
|
<STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
|
||||||
|
<STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
|
||||||
|
<STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
|
||||||
|
<STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
|
||||||
|
<STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
|
||||||
|
<STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
|
||||||
|
<STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
|
||||||
|
<STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
|
||||||
|
<STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
|
||||||
|
bias-disable;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,124 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
|
||||||
|
* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of the
|
||||||
|
* License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively,
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use,
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "stm32f429.dtsi"
|
||||||
|
#include "stm32f429-pinctrl.dtsi"
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32F429i-DISCO board";
|
||||||
|
compatible = "st,stm32f429i-disco", "st,stm32f429";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "root=/dev/ram";
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x90000000 0x800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &usart1;
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
red {
|
||||||
|
gpios = <&gpiog 14 0>;
|
||||||
|
};
|
||||||
|
green {
|
||||||
|
gpios = <&gpiog 13 0>;
|
||||||
|
linux,default-trigger = "heartbeat";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
autorepeat;
|
||||||
|
button@0 {
|
||||||
|
label = "User";
|
||||||
|
linux,code = <KEY_HOME>;
|
||||||
|
gpios = <&gpioa 0 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* This turns on vbus for otg for host mode (dwc2) */
|
||||||
|
vcc5v_otg: vcc5v-otg-regulator {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
gpio = <&gpioc 4 0>;
|
||||||
|
regulator-name = "vcc5_host1";
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&clk_hse {
|
||||||
|
clock-frequency = <8000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&crc {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
assigned-clocks = <&rcc 1 CLK_RTC>;
|
||||||
|
assigned-clock-parents = <&rcc 1 CLK_LSI>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usart1 {
|
||||||
|
pinctrl-0 = <&usart1_pins_a>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbotg_hs {
|
||||||
|
compatible = "st,stm32f4x9-fsotg";
|
||||||
|
dr_mode = "host";
|
||||||
|
pinctrl-0 = <&usbotg_fs_pins_b>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
|
||||||
|
* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of the
|
||||||
|
* License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively,
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use,
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32f4-pinctrl.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
soc {
|
||||||
|
pinctrl: pin-controller {
|
||||||
|
compatible = "st,stm32f429-pinctrl";
|
||||||
|
|
||||||
|
gpioa: gpio@40020000 {
|
||||||
|
gpio-ranges = <&pinctrl 0 0 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiob: gpio@40020400 {
|
||||||
|
gpio-ranges = <&pinctrl 0 16 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioc: gpio@40020800 {
|
||||||
|
gpio-ranges = <&pinctrl 0 32 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiod: gpio@40020c00 {
|
||||||
|
gpio-ranges = <&pinctrl 0 48 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioe: gpio@40021000 {
|
||||||
|
gpio-ranges = <&pinctrl 0 64 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiof: gpio@40021400 {
|
||||||
|
gpio-ranges = <&pinctrl 0 80 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiog: gpio@40021800 {
|
||||||
|
gpio-ranges = <&pinctrl 0 96 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioh: gpio@40021c00 {
|
||||||
|
gpio-ranges = <&pinctrl 0 112 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioi: gpio@40022000 {
|
||||||
|
gpio-ranges = <&pinctrl 0 128 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioj: gpio@40022400 {
|
||||||
|
gpio-ranges = <&pinctrl 0 144 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiok: gpio@40022800 {
|
||||||
|
gpio-ranges = <&pinctrl 0 160 8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,699 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
|
||||||
|
* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of the
|
||||||
|
* License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively,
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use,
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "skeleton.dtsi"
|
||||||
|
#include "armv7-m.dtsi"
|
||||||
|
#include <dt-bindings/clock/stm32fx-clock.h>
|
||||||
|
#include <dt-bindings/mfd/stm32f4-rcc.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
clocks {
|
||||||
|
clk_hse: clk-hse {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_lse: clk-lse {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <32768>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_lsi: clk-lsi {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <32000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_i2s_ckin: i2s-ckin {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
timer2: timer@40000000 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40000000 0x400>;
|
||||||
|
interrupts = <28>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers2: timers@40000000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40000000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@1 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3: timer@40000400 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40000400 0x400>;
|
||||||
|
interrupts = <29>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers3: timers@40000400 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40000400 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@2 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer4: timer@40000800 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40000800 0x400>;
|
||||||
|
interrupts = <30>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers4: timers@40000800 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40000800 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@3 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <3>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer5: timer@40000c00 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40000c00 0x400>;
|
||||||
|
interrupts = <50>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timers5: timers@40000c00 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40000C00 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@4 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer6: timer@40001000 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40001000 0x400>;
|
||||||
|
interrupts = <54>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers6: timers@40001000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40001000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
timer@5 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <5>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer7: timer@40001400 {
|
||||||
|
compatible = "st,stm32-timer";
|
||||||
|
reg = <0x40001400 0x400>;
|
||||||
|
interrupts = <55>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers7: timers@40001400 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40001400 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
timer@6 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <6>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers12: timers@40001800 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40001800 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@11 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <11>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers13: timers@40001c00 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40001C00 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers14: timers@40002000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40002000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc: rtc@40002800 {
|
||||||
|
compatible = "st,stm32-rtc";
|
||||||
|
reg = <0x40002800 0x400>;
|
||||||
|
clocks = <&rcc 1 CLK_RTC>;
|
||||||
|
clock-names = "ck_rtc";
|
||||||
|
assigned-clocks = <&rcc 1 CLK_RTC>;
|
||||||
|
assigned-clock-parents = <&rcc 1 CLK_LSE>;
|
||||||
|
interrupt-parent = <&exti>;
|
||||||
|
interrupts = <17 1>;
|
||||||
|
interrupt-names = "alarm";
|
||||||
|
st,syscfg = <&pwrcfg>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
iwdg: watchdog@40003000 {
|
||||||
|
compatible = "st,stm32-iwdg";
|
||||||
|
reg = <0x40003000 0x400>;
|
||||||
|
clocks = <&clk_lsi>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart2: serial@40004400 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40004400 0x400>;
|
||||||
|
interrupts = <38>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart3: serial@40004800 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40004800 0x400>;
|
||||||
|
interrupts = <39>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
|
||||||
|
status = "disabled";
|
||||||
|
dmas = <&dma1 1 4 0x400 0x0>,
|
||||||
|
<&dma1 3 4 0x400 0x0>;
|
||||||
|
dma-names = "rx", "tx";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart4: serial@40004c00 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40004c00 0x400>;
|
||||||
|
interrupts = <52>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart5: serial@40005000 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40005000 0x400>;
|
||||||
|
interrupts = <53>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: i2c@40005400 {
|
||||||
|
compatible = "st,stm32f4-i2c";
|
||||||
|
reg = <0x40005400 0x400>;
|
||||||
|
interrupts = <31>,
|
||||||
|
<32>;
|
||||||
|
resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
dac: dac@40007400 {
|
||||||
|
compatible = "st,stm32f4-dac-core";
|
||||||
|
reg = <0x40007400 0x400>;
|
||||||
|
resets = <&rcc STM32F4_APB1_RESET(DAC)>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
|
||||||
|
clock-names = "pclk";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
dac1: dac@1 {
|
||||||
|
compatible = "st,stm32-dac";
|
||||||
|
#io-channels-cells = <1>;
|
||||||
|
reg = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
dac2: dac@2 {
|
||||||
|
compatible = "st,stm32-dac";
|
||||||
|
#io-channels-cells = <1>;
|
||||||
|
reg = <2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usart7: serial@40007800 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40007800 0x400>;
|
||||||
|
interrupts = <82>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart8: serial@40007c00 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40007c00 0x400>;
|
||||||
|
interrupts = <83>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timers1: timers@40010000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40010000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@0 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers8: timers@40010400 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40010400 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@7 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <7>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usart1: serial@40011000 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40011000 0x400>;
|
||||||
|
interrupts = <37>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
|
||||||
|
status = "disabled";
|
||||||
|
dmas = <&dma2 2 4 0x400 0x0>,
|
||||||
|
<&dma2 7 4 0x400 0x0>;
|
||||||
|
dma-names = "rx", "tx";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart6: serial@40011400 {
|
||||||
|
compatible = "st,stm32-uart";
|
||||||
|
reg = <0x40011400 0x400>;
|
||||||
|
interrupts = <71>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
adc: adc@40012000 {
|
||||||
|
compatible = "st,stm32f4-adc-core";
|
||||||
|
reg = <0x40012000 0x400>;
|
||||||
|
interrupts = <18>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
||||||
|
clock-names = "adc";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
adc1: adc@0 {
|
||||||
|
compatible = "st,stm32f4-adc";
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
||||||
|
interrupt-parent = <&adc>;
|
||||||
|
interrupts = <0>;
|
||||||
|
dmas = <&dma2 0 0 0x400 0x0>;
|
||||||
|
dma-names = "rx";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
adc2: adc@100 {
|
||||||
|
compatible = "st,stm32f4-adc";
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
reg = <0x100>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
|
||||||
|
interrupt-parent = <&adc>;
|
||||||
|
interrupts = <1>;
|
||||||
|
dmas = <&dma2 3 1 0x400 0x0>;
|
||||||
|
dma-names = "rx";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
adc3: adc@200 {
|
||||||
|
compatible = "st,stm32f4-adc";
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
reg = <0x200>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
|
||||||
|
interrupt-parent = <&adc>;
|
||||||
|
interrupts = <2>;
|
||||||
|
dmas = <&dma2 1 2 0x400 0x0>;
|
||||||
|
dma-names = "rx";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
syscfg: system-config@40013800 {
|
||||||
|
compatible = "syscon";
|
||||||
|
reg = <0x40013800 0x400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
exti: interrupt-controller@40013c00 {
|
||||||
|
compatible = "st,stm32-exti";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x40013C00 0x400>;
|
||||||
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timers9: timers@40014000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40014000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@8 {
|
||||||
|
compatible = "st,stm32-timer-trigger";
|
||||||
|
reg = <8>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers10: timers@40014400 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40014400 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timers11: timers@40014800 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "st,stm32-timers";
|
||||||
|
reg = <0x40014800 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
|
||||||
|
clock-names = "int";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pwrcfg: power-config@40007000 {
|
||||||
|
compatible = "syscon";
|
||||||
|
reg = <0x40007000 0x400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ltdc: display-controller@40016800 {
|
||||||
|
compatible = "st,stm32-ltdc";
|
||||||
|
reg = <0x40016800 0x200>;
|
||||||
|
interrupts = <88>, <89>;
|
||||||
|
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||||
|
clocks = <&rcc 1 CLK_LCD>;
|
||||||
|
clock-names = "lcd";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
crc: crc@40023000 {
|
||||||
|
compatible = "st,stm32f4-crc";
|
||||||
|
reg = <0x40023000 0x400>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
rcc: rcc@40023810 {
|
||||||
|
#reset-cells = <1>;
|
||||||
|
#clock-cells = <2>;
|
||||||
|
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||||
|
reg = <0x40023800 0x400>;
|
||||||
|
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||||
|
st,syscfg = <&pwrcfg>;
|
||||||
|
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
||||||
|
assigned-clock-rates = <1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma1: dma-controller@40026000 {
|
||||||
|
compatible = "st,stm32-dma";
|
||||||
|
reg = <0x40026000 0x400>;
|
||||||
|
interrupts = <11>,
|
||||||
|
<12>,
|
||||||
|
<13>,
|
||||||
|
<14>,
|
||||||
|
<15>,
|
||||||
|
<16>,
|
||||||
|
<17>,
|
||||||
|
<47>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
|
||||||
|
#dma-cells = <4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma2: dma-controller@40026400 {
|
||||||
|
compatible = "st,stm32-dma";
|
||||||
|
reg = <0x40026400 0x400>;
|
||||||
|
interrupts = <56>,
|
||||||
|
<57>,
|
||||||
|
<58>,
|
||||||
|
<59>,
|
||||||
|
<60>,
|
||||||
|
<68>,
|
||||||
|
<69>,
|
||||||
|
<70>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
|
||||||
|
#dma-cells = <4>;
|
||||||
|
st,mem2mem;
|
||||||
|
};
|
||||||
|
|
||||||
|
mac: ethernet@40028000 {
|
||||||
|
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
|
||||||
|
reg = <0x40028000 0x8000>;
|
||||||
|
reg-names = "stmmaceth";
|
||||||
|
interrupts = <61>;
|
||||||
|
interrupt-names = "macirq";
|
||||||
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
|
||||||
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
|
||||||
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
|
||||||
|
st,syscon = <&syscfg 0x4>;
|
||||||
|
snps,pbl = <8>;
|
||||||
|
snps,mixed-burst;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usbotg_hs: usb@40040000 {
|
||||||
|
compatible = "snps,dwc2";
|
||||||
|
reg = <0x40040000 0x40000>;
|
||||||
|
interrupts = <77>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
|
||||||
|
clock-names = "otg";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usbotg_fs: usb@50000000 {
|
||||||
|
compatible = "st,stm32f4x9-fsotg";
|
||||||
|
reg = <0x50000000 0x40000>;
|
||||||
|
interrupts = <67>;
|
||||||
|
clocks = <&rcc 0 39>;
|
||||||
|
clock-names = "otg";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
dcmi: dcmi@50050000 {
|
||||||
|
compatible = "st,stm32-dcmi";
|
||||||
|
reg = <0x50050000 0x400>;
|
||||||
|
interrupts = <78>;
|
||||||
|
resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
|
||||||
|
clock-names = "mclk";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&dcmi_pins>;
|
||||||
|
dmas = <&dma2 1 1 0x414 0x3>;
|
||||||
|
dma-names = "tx";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
rng: rng@50060800 {
|
||||||
|
compatible = "st,stm32-rng";
|
||||||
|
reg = <0x50060800 0x400>;
|
||||||
|
interrupts = <80>;
|
||||||
|
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
|
||||||
|
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&systick {
|
||||||
|
clocks = <&rcc 1 SYSTICK>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,108 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* This header provides constants for the STM32F4 RCC IP
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
|
||||||
|
#define _DT_BINDINGS_MFD_STM32F4_RCC_H
|
||||||
|
|
||||||
|
/* AHB1 */
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOA 0
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOB 1
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOC 2
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOD 3
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOE 4
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOF 5
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOG 6
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOH 7
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOI 8
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOJ 9
|
||||||
|
#define STM32F4_RCC_AHB1_GPIOK 10
|
||||||
|
#define STM32F4_RCC_AHB1_CRC 12
|
||||||
|
#define STM32F4_RCC_AHB1_BKPSRAM 18
|
||||||
|
#define STM32F4_RCC_AHB1_CCMDATARAM 20
|
||||||
|
#define STM32F4_RCC_AHB1_DMA1 21
|
||||||
|
#define STM32F4_RCC_AHB1_DMA2 22
|
||||||
|
#define STM32F4_RCC_AHB1_DMA2D 23
|
||||||
|
#define STM32F4_RCC_AHB1_ETHMAC 25
|
||||||
|
#define STM32F4_RCC_AHB1_ETHMACTX 26
|
||||||
|
#define STM32F4_RCC_AHB1_ETHMACRX 27
|
||||||
|
#define STM32F4_RCC_AHB1_ETHMACPTP 28
|
||||||
|
#define STM32F4_RCC_AHB1_OTGHS 29
|
||||||
|
#define STM32F4_RCC_AHB1_OTGHSULPI 30
|
||||||
|
|
||||||
|
#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
|
||||||
|
#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
|
||||||
|
|
||||||
|
/* AHB2 */
|
||||||
|
#define STM32F4_RCC_AHB2_DCMI 0
|
||||||
|
#define STM32F4_RCC_AHB2_CRYP 4
|
||||||
|
#define STM32F4_RCC_AHB2_HASH 5
|
||||||
|
#define STM32F4_RCC_AHB2_RNG 6
|
||||||
|
#define STM32F4_RCC_AHB2_OTGFS 7
|
||||||
|
|
||||||
|
#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
|
||||||
|
#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
|
||||||
|
|
||||||
|
/* AHB3 */
|
||||||
|
#define STM32F4_RCC_AHB3_FMC 0
|
||||||
|
#define STM32F4_RCC_AHB3_QSPI 1
|
||||||
|
|
||||||
|
#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
|
||||||
|
#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
|
||||||
|
|
||||||
|
/* APB1 */
|
||||||
|
#define STM32F4_RCC_APB1_TIM2 0
|
||||||
|
#define STM32F4_RCC_APB1_TIM3 1
|
||||||
|
#define STM32F4_RCC_APB1_TIM4 2
|
||||||
|
#define STM32F4_RCC_APB1_TIM5 3
|
||||||
|
#define STM32F4_RCC_APB1_TIM6 4
|
||||||
|
#define STM32F4_RCC_APB1_TIM7 5
|
||||||
|
#define STM32F4_RCC_APB1_TIM12 6
|
||||||
|
#define STM32F4_RCC_APB1_TIM13 7
|
||||||
|
#define STM32F4_RCC_APB1_TIM14 8
|
||||||
|
#define STM32F4_RCC_APB1_WWDG 11
|
||||||
|
#define STM32F4_RCC_APB1_SPI2 14
|
||||||
|
#define STM32F4_RCC_APB1_SPI3 15
|
||||||
|
#define STM32F4_RCC_APB1_UART2 17
|
||||||
|
#define STM32F4_RCC_APB1_UART3 18
|
||||||
|
#define STM32F4_RCC_APB1_UART4 19
|
||||||
|
#define STM32F4_RCC_APB1_UART5 20
|
||||||
|
#define STM32F4_RCC_APB1_I2C1 21
|
||||||
|
#define STM32F4_RCC_APB1_I2C2 22
|
||||||
|
#define STM32F4_RCC_APB1_I2C3 23
|
||||||
|
#define STM32F4_RCC_APB1_CAN1 25
|
||||||
|
#define STM32F4_RCC_APB1_CAN2 26
|
||||||
|
#define STM32F4_RCC_APB1_PWR 28
|
||||||
|
#define STM32F4_RCC_APB1_DAC 29
|
||||||
|
#define STM32F4_RCC_APB1_UART7 30
|
||||||
|
#define STM32F4_RCC_APB1_UART8 31
|
||||||
|
|
||||||
|
#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
|
||||||
|
#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
|
||||||
|
|
||||||
|
/* APB2 */
|
||||||
|
#define STM32F4_RCC_APB2_TIM1 0
|
||||||
|
#define STM32F4_RCC_APB2_TIM8 1
|
||||||
|
#define STM32F4_RCC_APB2_USART1 4
|
||||||
|
#define STM32F4_RCC_APB2_USART6 5
|
||||||
|
#define STM32F4_RCC_APB2_ADC1 8
|
||||||
|
#define STM32F4_RCC_APB2_ADC2 9
|
||||||
|
#define STM32F4_RCC_APB2_ADC3 10
|
||||||
|
#define STM32F4_RCC_APB2_SDIO 11
|
||||||
|
#define STM32F4_RCC_APB2_SPI1 12
|
||||||
|
#define STM32F4_RCC_APB2_SPI4 13
|
||||||
|
#define STM32F4_RCC_APB2_SYSCFG 14
|
||||||
|
#define STM32F4_RCC_APB2_TIM9 16
|
||||||
|
#define STM32F4_RCC_APB2_TIM10 17
|
||||||
|
#define STM32F4_RCC_APB2_TIM11 18
|
||||||
|
#define STM32F4_RCC_APB2_SPI5 20
|
||||||
|
#define STM32F4_RCC_APB2_SPI6 21
|
||||||
|
#define STM32F4_RCC_APB2_SAI1 22
|
||||||
|
#define STM32F4_RCC_APB2_LTDC 26
|
||||||
|
#define STM32F4_RCC_APB2_DSI 27
|
||||||
|
|
||||||
|
#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
|
||||||
|
#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
|
||||||
|
|
||||||
|
#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
|
||||||
|
#define _DT_BINDINGS_STM32_PINFUNC_H
|
||||||
|
|
||||||
|
/* define PIN modes */
|
||||||
|
#define GPIO 0x0
|
||||||
|
#define AF0 0x1
|
||||||
|
#define AF1 0x2
|
||||||
|
#define AF2 0x3
|
||||||
|
#define AF3 0x4
|
||||||
|
#define AF4 0x5
|
||||||
|
#define AF5 0x6
|
||||||
|
#define AF6 0x7
|
||||||
|
#define AF7 0x8
|
||||||
|
#define AF8 0x9
|
||||||
|
#define AF9 0xa
|
||||||
|
#define AF10 0xb
|
||||||
|
#define AF11 0xc
|
||||||
|
#define AF12 0xd
|
||||||
|
#define AF13 0xe
|
||||||
|
#define AF14 0xf
|
||||||
|
#define AF15 0x10
|
||||||
|
#define ANALOG 0x11
|
||||||
|
|
||||||
|
/* define Pins number*/
|
||||||
|
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
|
||||||
|
|
||||||
|
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
|
||||||
|
|
||||||
|
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||||
|
|
||||||
Loading…
Reference in New Issue