ADD: [nrhw17] support for ptt module in u-boot and logic

BugzID: 52451

arch/arm/lib/bootm.c

@@ -416,6 +416,9 @@ static void setup_end_tag(bd_t *bd)
 #endif
 
 #ifdef CONFIG_OF_LIBFDT
+
+void nm_fdt_setup(void *blob);
+
 static int create_fdt(bootm_headers_t *images)
 {
 	ulong of_size = images->ft_len;
@@ -459,6 +462,8 @@ static int create_fdt(bootm_headers_t *images)
 #ifdef CONFIG_OF_BOARD_SETUP
 	if (!skip)
 		ft_board_setup(*of_flat_tree, gd->bd);
+
+	nm_fdt_setup(*of_flat_tree);
 #endif
 
 	return 0;

board/mv_ebu/a38x/nbhw14/nbhw14_init.c

@@ -356,3 +356,7 @@ void nbhw_phy_init(void)
 	}
 }
 
+void nm_fdt_setup(void *blob)
+{
+	/* Nothing to do */
+}

board/mv_ebu/a38x/nbhw17/nbhw17_fpga_regs.h

@@ -837,5 +837,9 @@ PCM data from PCIe slot is written to TX buffer and PCM data from CPU is written
 #define VTIS_IDLE_MASK	(0xffffUL)
 #define VTIS_IDLE_ACCESS	(READ_WRITE)
 
+/*** Slot 1 GPIO pin config ***/
+#define PCIE_4_PCM_GPIO_EN	(0x0430)
+#define PCIE_4_PCM_GPIO_DIR	(0x0432)
+#define PCIE_4_PCM_GPIO_DAT	(0x0434)
 
 #endif /* NBHW17_FPGA_REGS_H */

board/mv_ebu/a38x/nbhw17/nbhw17_init.c

@@ -14,10 +14,13 @@
  *****************************************************************************/
 /* #define DEBUG */
 #include <environment.h>
+#include <libfdt.h>
 #include <u-boot/md5.h>
 
 #include "config.h"
+#include "nbhw.h"
 #include "nbhw17_gpio.h"
+#include "nbhw17_fpga_regs.h"
 #include "../nbhw_init.h"
 #include "../nbhw_bd.h"
 #include "../nbhw_fpga_prog.h"
@@ -283,3 +286,47 @@ void nbhw_phy_init(void)
 		check_pcie_wlan_modules();
 	}
 }
+
+
+/*******************************************************************************
+	Enable additional nodes in DTS depending on board descriptor
+*******************************************************************************/
+
+static void ft_enable_node(void* blob, const char* name)
+{
+	int node_ofs = -1;
+
+	node_ofs = fdt_path_offset(blob, name);
+	if (node_ofs >= 0) {
+		fdt_setprop_string(blob, node_ofs, "status", "okay");
+	}
+}
+
+static void ft_netbox_dio_ptt_4(void *blob)
+{
+	printf("FT: enable netbox_dio_ptt_4\n");
+
+	ft_enable_node(blob, "/netbox_dio_ptt_4");
+
+	// also reconfigure PCM lines in FPGA as GPIOs
+	FPGA_REG(PCIE_4_PCM_GPIO_EN) = 0x0001;  /* Enable GPIO functionality for slot 4 */
+	FPGA_REG(PCIE_4_PCM_GPIO_DIR) = 0x0004; /* Set GPIO directions */
+	FPGA_REG(PCIE_4_PCM_GPIO_DAT) = 0; /* Set output to 0 */
+}
+
+void nm_fdt_setup(void *blob)
+{
+	int module;
+	char* slotDescr = "slot=3";
+	char pdValue[200];
+	for (module=0; module<4; module++) {
+		pdValue[0] = 0;  /*init with an empty string*/
+		if (bd_get_pd_module(module, pdValue, sizeof(pdValue))==0) {
+			/* We have a PTT module with gpios in slot 4, so enable it  */
+			if ((strstr(pdValue, slotDescr)) && (strstr(pdValue, "dio-x1")))
+				ft_netbox_dio_ptt_4(blob);
+		}
+	}
+}
+
+

board/mv_ebu/a38x/nbhw18/nbhw18_init.c

@@ -406,3 +406,8 @@ void nbhw_phy_init(void)
 	configure_switch();
 #endif
 }
+
+void nm_fdt_setup(void *blob)
+{
+	/* Nothing to do */
+}

lib/sha256.c

@@ -270,7 +270,7 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
 {
 	sha256_context ctx;
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
-	unsigned char *end, *curr;
+	const unsigned char *end, *curr;
 	int chunk;
 #endif