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arm: zynq: Rework FPGA initialization 

This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2018-01-17 10:56:22 -03:00
parent 57213c5f37
commit 4aba5fb857
5 changed files with 100 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -821,6 +821,7 @@ config ARCH_ZYNQ
imply CMD_CLK imply CMD_CLK
imply FAT_WRITE imply FAT_WRITE
imply CMD_SPL imply CMD_SPL
imply ARCH_EARLY_INIT_R
config ARCH_ZYNQMP config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform" bool "Xilinx ZynqMP based platform"

66
arch/arm/mach-zynq/cpu.c
View File

@ -4,14 +4,45 @@
* Copyright (C) 2012 Xilinx, Inc. All rights reserved. * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*/ */
#include <common.h> #include <common.h>
#include <zynqpl.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/arch/ps7_init_gpl.h>
#include <asm/arch/sys_proto.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28 #define ZYNQ_SILICON_VER_SHIFT 28
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
};
#endif
static const struct {
u8 idcode;
#if defined(CONFIG_FPGA)
u32 fpga_size;
#endif
char *devicename;
} zynq_fpga_descs[] = {
ZYNQ_DESC(7Z007S),
ZYNQ_DESC(7Z010),
ZYNQ_DESC(7Z012S),
ZYNQ_DESC(7Z014S),
ZYNQ_DESC(7Z015),
ZYNQ_DESC(7Z020),
ZYNQ_DESC(7Z030),
ZYNQ_DESC(7Z035),
ZYNQ_DESC(7Z045),
ZYNQ_DESC(7Z100),
{ /* Sentinel */ },
};
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
zynq_slcr_unlock(); zynq_slcr_unlock();
@ -59,3 +90,36 @@ void enable_caches(void)
dcache_enable(); dcache_enable();
} }
#endif #endif
static int __maybe_unused cpu_desc_id(void)
{
u32 idcode;
u8 i;
idcode = zynq_slcr_get_idcode();
for (i = 0; zynq_fpga_descs[i].idcode; i++) {
if (zynq_fpga_descs[i].idcode == idcode)
return i;
}
return -ENODEV;
}
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
int cpu_id = cpu_desc_id();
if (cpu_id < 0)
return 0;
fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
fpga.name = zynq_fpga_descs[cpu_id].devicename;
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
#endif

63
board/xilinx/zynq/board.c
View File

@ -17,23 +17,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
static xilinx_desc fpga;
/* It can be done differently */
static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
static struct udevice *watchdog_dev; static struct udevice *watchdog_dev;
#endif #endif
@ -52,46 +35,6 @@ int board_early_init_f(void)
int board_init(void) int board_init(void)
{ {
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7007S:
fpga = fpga007s;
break;
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7012S:
fpga = fpga012s;
break;
case XILINX_ZYNQ_7014S:
fpga = fpga014s;
break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7035:
fpga = fpga035;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
puts("Watchdog: Not found!\n"); puts("Watchdog: Not found!\n");
@ -101,12 +44,6 @@ int board_init(void)
} }
# endif # endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0; return 0;
} }

1
configs/zynq_cse_qspi_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-1 CONFIG_BOOTDELAY=-1
# CONFIG_USE_BOOTCOMMAND is not set # CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> " CONFIG_SYS_PROMPT="Zynq> "

87
include/zynqpl.h
View File

@ -11,23 +11,18 @@
#include <xilinx.h> #include <xilinx.h>
#if defined(CONFIG_FPGA_ZYNQPL)
extern struct xilinx_fpga_op zynq_op; extern struct xilinx_fpga_op zynq_op;
# define FPGA_ZYNQPL_OPS &zynq_op
#else
# define FPGA_ZYNQPL_OPS NULL
#endif
#define XILINX_ZYNQ_7007S 0x3 #define XILINX_ZYNQ_XC7Z007S 0x3
#define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_XC7Z010 0x2
#define XILINX_ZYNQ_7012S 0x1c #define XILINX_ZYNQ_XC7Z012S 0x1c
#define XILINX_ZYNQ_7014S 0x8 #define XILINX_ZYNQ_XC7Z014S 0x8
#define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_XC7Z015 0x1b
#define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_XC7Z020 0x7
#define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_XC7Z030 0xc
#define XILINX_ZYNQ_7035 0x12 #define XILINX_ZYNQ_XC7Z035 0x12
#define XILINX_ZYNQ_7045 0x11 #define XILINX_ZYNQ_XC7Z045 0x11
#define XILINX_ZYNQ_7100 0x16 #define XILINX_ZYNQ_XC7Z100 0x16
/* Device Image Sizes */ /* Device Image Sizes */
#define XILINX_XC7Z007S_SIZE 16669920/8 #define XILINX_XC7Z007S_SIZE 16669920/8
@ -41,45 +36,29 @@ extern struct xilinx_fpga_op zynq_op;
#define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8 #define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */ /* Device Names */
#define XILINX_XC7Z007S_DESC(cookie) \ #define XILINX_XC7Z007S_NAME "7z007s"
{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ #define XILINX_XC7Z010_NAME "7z010"
"7z007s" } #define XILINX_XC7Z012S_NAME "7z012s"
#define XILINX_XC7Z014S_NAME "7z014s"
#define XILINX_XC7Z015_NAME "7z015"
#define XILINX_XC7Z020_NAME "7z020"
#define XILINX_XC7Z030_NAME "7z030"
#define XILINX_XC7Z035_NAME "7z035"
#define XILINX_XC7Z045_NAME "7z045"
#define XILINX_XC7Z100_NAME "7z100"
#define XILINX_XC7Z010_DESC(cookie) \ #if defined(CONFIG_FPGA)
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ #define ZYNQ_DESC(name) { \
"7z010" } .idcode = XILINX_ZYNQ_XC##name, \
.fpga_size = XILINX_XC##name##_SIZE, \
#define XILINX_XC7Z012S_DESC(cookie) \ .devicename = XILINX_XC##name##_NAME \
{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ }
"7z012s" } #else
#define ZYNQ_DESC(name) { \
#define XILINX_XC7Z014S_DESC(cookie) \ .idcode = XILINX_ZYNQ_XC##name, \
{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ .devicename = XILINX_XC##name##_NAME \
"7z014s" } }
#endif
#define XILINX_XC7Z015_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z030" }
#define XILINX_XC7Z035_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z035" }
#define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z100" }
#endif /* _ZYNQPL_H_ */ #endif /* _ZYNQPL_H_ */