omap3: Add interface for omap3 DMA
Adds an interface to use the OMAP3 DMA. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Simon Schwarz
Albert ARIBAUD
parent
7b646a6d12
commit
4c4bb19d05
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@ -0,0 +1,77 @@
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#ifndef __SDMA_H
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#define __SDMA_H
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/* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Functions */
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void omap3_dma_init(void);
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze);
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int omap3_dma_start_transfer(uint32_t chan);
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int omap3_dma_wait_for_transfer(uint32_t chan);
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
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/* Register settings */
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#define CSDP_DATA_TYPE_8BIT 0x0
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#define CSDP_DATA_TYPE_16BIT 0x1
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#define CSDP_DATA_TYPE_32BIT 0x2
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#define CSDP_SRC_BURST_SINGLE (0x0 << 7)
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#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7)
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#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7)
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#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7)
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#define CSDP_DST_BURST_SINGLE (0x0 << 14)
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#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14)
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#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14)
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#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14)
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#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18)
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#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18)
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#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19)
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#define CSDP_DST_ENDIAN_BIG (0x1 << 19)
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#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20)
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#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20)
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#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21)
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#define CSDP_SRC_ENDIAN_BIG (0x1 << 21)
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#define CCR_READ_PRIORITY_LOW (0x0 << 6)
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#define CCR_READ_PRIORITY_HIGH (0x1 << 6)
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#define CCR_ENABLE_DISABLED (0x0 << 7)
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#define CCR_ENABLE_ENABLE (0x1 << 7)
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#define CCR_SRC_AMODE_CONSTANT (0x0 << 12)
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#define CCR_SRC_AMODE_POST_INC (0x1 << 12)
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#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12)
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#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12)
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#define CCR_DST_AMODE_CONSTANT (0x0 << 14)
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#define CCR_DST_AMODE_POST_INC (0x1 << 14)
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#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14)
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#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14)
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#define CCR_RD_ACTIVE_MASK (1 << 9)
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#define CCR_WR_ACTIVE_MASK (1 << 10)
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#define CSR_TRANS_ERR (1 << 8)
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#define CSR_SUPERVISOR_ERR (1 << 10)
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#define CSR_MISALIGNED_ADRS_ERR (1 << 11)
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/* others */
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#define CHAN_NR_MIN 0
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#define CHAN_NR_MAX 31
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#endif /* __SDMA_H */
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@ -95,6 +95,7 @@ Interfaces
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==========
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==========
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gpio
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gpio
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----
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To set a bit :
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To set a bit :
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@ -122,6 +123,23 @@ To read a bit :
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else
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else
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printf("GPIO N is clear\n");
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printf("GPIO N is clear\n");
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dma
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---
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void omap3_dma_init(void)
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Init the DMA module
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
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Read config of the channel
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
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Write config to the channel
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze)
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Config source, destination and size of a transfer
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int omap3_dma_wait_for_transfer(uint32_t chan)
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Wait for a transfer to end - this hast to be called before a channel
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or the data the channel transferd are used.
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int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
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Read silicon Revision of the DMA module
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Acknowledgements
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Acknowledgements
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================
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================
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@ -27,6 +27,7 @@ LIB := $(obj)libdma.o
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COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
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COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
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COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
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COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
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COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
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COBJS := $(COBJS-y)
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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SRCS := $(COBJS:.o=.c)
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@ -0,0 +1,180 @@
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/* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3
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* Tested on Silicon Revision major:0x4 minor:0x0
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap3.h>
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#include <asm/arch/dma.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE;
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uint32_t dma_active; /* if a transfer is started the respective
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bit is set for the logical channel */
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/* Check if we have the given channel
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* PARAMETERS:
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* chan: Channel number
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*
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* RETURN of non-zero means error */
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static inline int check_channel(uint32_t chan)
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{
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if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX)
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return -EINVAL;
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return 0;
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}
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static inline void reset_irq(uint32_t chan)
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{
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/* reset IRQ reason */
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writel(0x1DFE, &dma4_cfg->chan[chan].csr);
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/* reset IRQ */
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writel((1 << chan), &dma4_cfg->irqstatus_l[0]);
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dma_active &= ~(1 << chan);
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}
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/* Set Source, Destination and Size of DMA transfer for the
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* specified channel.
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* PARAMETERS:
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* chan: channel to use
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* src: source of the transfer
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* dst: destination of the transfer
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* sze: Size of the transfer
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*
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* RETURN of non-zero means error */
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze)
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{
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if (check_channel(chan))
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return -EINVAL;
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/* CDSA0 */
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writel((uint32_t)src, &dma4_cfg->chan[chan].cssa);
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writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa);
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writel(sze, &dma4_cfg->chan[chan].cen);
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return 0;
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}
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/* Start the DMA transfer */
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int omap3_dma_start_transfer(uint32_t chan)
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{
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uint32_t val;
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if (check_channel(chan))
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return -EINVAL;
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val = readl(&dma4_cfg->chan[chan].ccr);
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/* Test for channel already in use */
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if (val & CCR_ENABLE_ENABLE)
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return -EBUSY;
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writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr);
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dma_active |= (1 << chan);
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debug("started transfer...\n");
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return 0;
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}
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/* Busy-waiting for a DMA transfer
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* This has to be called before another transfer is started
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* PARAMETER
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* chan: Channel to wait for
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*
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* RETURN of non-zero means error*/
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int omap3_dma_wait_for_transfer(uint32_t chan)
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{
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uint32_t val;
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if (!(dma_active & (1 << chan))) {
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val = readl(&dma4_cfg->irqstatus_l[0]);
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if (!(val & chan)) {
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debug("dma: The channel you are trying to wait for "
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"was never activated - ERROR\n");
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return -1; /* channel was never active */
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}
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}
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/* all irqs on line 0 */
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while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan)))
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asm("nop");
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val = readl(&dma4_cfg->chan[chan].csr);
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if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) |
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(val & CSR_MISALIGNED_ADRS_ERR)) {
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debug("err code: %X\n", val);
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debug("dma: transfer error detected\n");
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reset_irq(chan);
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return -1;
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}
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reset_irq(chan);
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return 0;
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}
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/* Get the revision of the DMA module
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* PARAMETER
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* minor: Address of minor revision to write
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* major: Address of major revision to write
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*
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* RETURN of non-zero means error
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*/
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int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
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{
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uint32_t val;
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/* debug information */
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val = readl(&dma4_cfg->revision);
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*major = (val & 0x000000F0) >> 4;
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*minor = (val & 0x0000000F);
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debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor);
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return 0;
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}
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/* Initial config of omap dma
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*/
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void omap3_dma_init(void)
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{
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dma_active = 0;
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/* All interrupts on channel 0 */
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writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]);
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}
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/* set channel config to config
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*
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* RETURN of non-zero means error */
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config)
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{
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if (check_channel(chan))
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return -EINVAL;
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dma4_cfg->chan[chan] = *config;
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return 0;
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}
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/* get channel config to config
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*
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* RETURN of non-zero means error */
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config)
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{
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if (check_channel(chan))
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return -EINVAL;
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*config = dma4_cfg->chan[chan];
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return 0;
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}
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