Merge branch '2022-08-31-assorted-fixes'
- Assorted bugfixes including re-working the i2c command CVE and fixing some TI reference platforms with different EEPROMs.
This commit is contained in:
Tom Rini
commit
4e10c1227a
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|
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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|
||||
# Grab our configured image. The source for this is found at:
|
||||
# https://source.denx.de/u-boot/gitlab-ci-runner
|
||||
# Grab our configured image. The source for this is found
|
||||
# in the u-boot tree at tools/docker/Dockerfile
|
||||
image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022
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|
||||
# We run some tests in different order, to catch some failures quicker.
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||||
|
|
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|
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@ -32,12 +32,12 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
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{
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register long result asm("r0");
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#if defined(CONFIG_ARM64)
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asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
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asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
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#elif defined(CONFIG_CPU_V7M)
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asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
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asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
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#else
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/* Note - untested placeholder */
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asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
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asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
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#endif
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return result;
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}
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@ -86,7 +86,6 @@ __weak void gpi2c_init(void)
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static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
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u32 header, u32 size, uint8_t *ep)
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{
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u32 hdr_read = 0xdeadbeef;
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int rc;
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#if CONFIG_IS_ENABLED(DM_I2C)
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@ -113,10 +112,10 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
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* We must allow for fall through to check the data if 2 byte
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* addressing works
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*/
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(void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
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(void)dm_i2c_read(dev, 0, ep, size);
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/* Corrupted data??? */
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if (hdr_read != header) {
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if (*((u32 *)ep) != header) {
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/*
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* read the eeprom header using i2c again, but use only a
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* 2 byte address (some newer boards need this..)
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@ -125,16 +124,12 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
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if (rc)
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return rc;
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rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
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if (rc)
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return rc;
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}
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if (hdr_read != header)
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return -1;
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rc = dm_i2c_read(dev, 0, ep, size);
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if (rc)
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return rc;
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}
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if (*((u32 *)ep) != header)
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return -1;
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#else
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u32 byte;
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@ -154,26 +149,21 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
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* We must allow for fall through to check the data if 2 byte
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* addressing works
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*/
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(void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
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(void)i2c_read(dev_addr, 0x0, byte, ep, size);
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/* Corrupted data??? */
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if (hdr_read != header) {
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if (*((u32 *)ep) != header) {
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/*
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* read the eeprom header using i2c again, but use only a
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* 2 byte address (some newer boards need this..)
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*/
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byte = 2;
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rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
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4);
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if (rc)
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return rc;
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}
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if (hdr_read != header)
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return -1;
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rc = i2c_read(dev_addr, 0x0, byte, ep, size);
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if (rc)
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return rc;
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}
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if (*((u32 *)ep) != header)
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return -1;
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#endif
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return 0;
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}
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16
boot/bootm.c
16
boot/bootm.c
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@ -305,9 +305,9 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start,
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/* check if FDT overlaps OS image */
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if (images.ft_addr &&
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(((ulong)images.ft_addr >= start &&
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(ulong)images.ft_addr <= start + size) ||
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(ulong)images.ft_addr < start + size) ||
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((ulong)images.ft_addr + images.ft_len >= start &&
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(ulong)images.ft_addr + images.ft_len <= start + size))) {
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(ulong)images.ft_addr + images.ft_len < start + size))) {
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printf("ERROR: FDT image overlaps OS image (OS=0x%lx..0x%lx)\n",
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start, start + size);
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return 1;
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@ -1006,7 +1006,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type,
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int noffset;
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ulong load_end, buf_size;
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uint8_t image_type;
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uint8_t imape_comp;
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uint8_t image_comp;
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void *load_buf;
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int ret;
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@ -1024,20 +1024,18 @@ static int bootm_host_load_image(const void *fit, int req_image_type,
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return -EINVAL;
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}
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if (fit_image_get_comp(fit, noffset, &imape_comp)) {
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puts("Can't get image compression!\n");
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return -EINVAL;
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}
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if (fit_image_get_comp(fit, noffset, &image_comp))
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image_comp = IH_COMP_NONE;
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/* Allow the image to expand by a factor of 4, should be safe */
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buf_size = (1 << 20) + len * 4;
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load_buf = malloc(buf_size);
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ret = image_decomp(imape_comp, 0, data, image_type, load_buf,
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ret = image_decomp(image_comp, 0, data, image_type, load_buf,
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(void *)data, len, buf_size, &load_end);
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free(load_buf);
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if (ret) {
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ret = handle_decomp_error(imape_comp, load_end - 0, buf_size, ret);
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ret = handle_decomp_error(image_comp, load_end - 0, buf_size, ret);
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if (ret != BOOTM_ERR_UNIMPLEMENTED)
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return ret;
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}
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@ -477,7 +477,7 @@ void fit_print_contents(const void *fit)
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void fit_image_print(const void *fit, int image_noffset, const char *p)
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{
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char *desc;
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uint8_t type, arch, os, comp;
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uint8_t type, arch, os, comp = IH_COMP_NONE;
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size_t size;
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ulong load, entry;
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const void *data;
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@ -794,7 +794,6 @@ int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp)
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data = fdt_getprop(fit, noffset, FIT_COMP_PROP, &len);
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if (data == NULL) {
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fit_get_debug(fit, noffset, FIT_COMP_PROP, len);
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*comp = -1;
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return -1;
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}
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25
cmd/i2c.c
25
cmd/i2c.c
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@ -200,10 +200,10 @@ void i2c_init_board(void)
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*
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* Returns the address length.
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*/
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static uint get_alen(char *arg, uint default_len)
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static uint get_alen(char *arg, int default_len)
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{
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uint j;
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uint alen;
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int j;
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int alen;
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alen = default_len;
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for (j = 0; j < 8; j++) {
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@ -247,7 +247,7 @@ static int do_i2c_read(struct cmd_tbl *cmdtp, int flag, int argc,
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{
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uint chip;
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uint devaddr, length;
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uint alen;
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int alen;
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u_char *memaddr;
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int ret;
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#if CONFIG_IS_ENABLED(DM_I2C)
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@ -301,7 +301,7 @@ static int do_i2c_write(struct cmd_tbl *cmdtp, int flag, int argc,
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{
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uint chip;
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uint devaddr, length;
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uint alen;
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int alen;
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u_char *memaddr;
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int ret;
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#if CONFIG_IS_ENABLED(DM_I2C)
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@ -469,8 +469,9 @@ static int do_i2c_md(struct cmd_tbl *cmdtp, int flag, int argc,
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{
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uint chip;
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uint addr, length;
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uint alen;
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uint j, nbytes, linebytes;
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int alen;
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int j;
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uint nbytes, linebytes;
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int ret;
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct udevice *dev;
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@ -589,9 +590,9 @@ static int do_i2c_mw(struct cmd_tbl *cmdtp, int flag, int argc,
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{
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uint chip;
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ulong addr;
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uint alen;
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int alen;
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uchar byte;
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uint count;
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int count;
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int ret;
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct udevice *dev;
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@ -676,8 +677,8 @@ static int do_i2c_crc(struct cmd_tbl *cmdtp, int flag, int argc,
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{
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uint chip;
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ulong addr;
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uint alen;
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uint count;
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int alen;
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int count;
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uchar byte;
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ulong crc;
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ulong err;
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@ -985,7 +986,7 @@ static int do_i2c_loop(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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uint chip;
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uint alen;
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int alen;
|
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uint addr;
|
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uint length;
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u_char bytes[16];
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|
|
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@ -171,11 +171,8 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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return 1;
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}
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|
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if (fit_image_get_comp(fit_hdr, noffset, &comp)) {
|
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puts("Could not find script subimage "
|
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"compression type\n");
|
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return 1;
|
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}
|
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if (fit_image_get_comp(fit_hdr, noffset, &comp))
|
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comp = IH_COMP_NONE;
|
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|
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data = (ulong)fit_data;
|
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len = (ulong)fit_len;
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|
|
|
|||
|
|
@ -600,6 +600,9 @@ static void pre_console_putc(const char c)
|
|||
{
|
||||
char *buffer;
|
||||
|
||||
if (gd->precon_buf_idx < 0)
|
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return;
|
||||
|
||||
buffer = map_sysmem(CONFIG_VAL(PRE_CON_BUF_ADDR), CONFIG_VAL(PRE_CON_BUF_SZ));
|
||||
|
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buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c;
|
||||
|
|
@ -609,13 +612,16 @@ static void pre_console_putc(const char c)
|
|||
|
||||
static void pre_console_puts(const char *s)
|
||||
{
|
||||
if (gd->precon_buf_idx < 0)
|
||||
return;
|
||||
|
||||
while (*s)
|
||||
pre_console_putc(*s++);
|
||||
}
|
||||
|
||||
static void print_pre_console_buffer(int flushpoint)
|
||||
{
|
||||
unsigned long in = 0, out = 0;
|
||||
long in = 0, out = 0;
|
||||
char buf_out[CONFIG_VAL(PRE_CON_BUF_SZ) + 1];
|
||||
char *buf_in;
|
||||
|
||||
|
|
@ -632,6 +638,7 @@ static void print_pre_console_buffer(int flushpoint)
|
|||
|
||||
buf_out[out] = 0;
|
||||
|
||||
gd->precon_buf_idx = -1;
|
||||
switch (flushpoint) {
|
||||
case PRE_CONSOLE_FLUSHPOINT1_SERIAL:
|
||||
puts(buf_out);
|
||||
|
|
@ -640,6 +647,7 @@ static void print_pre_console_buffer(int flushpoint)
|
|||
console_puts_select(stdout, false, buf_out);
|
||||
break;
|
||||
}
|
||||
gd->precon_buf_idx = in;
|
||||
}
|
||||
#else
|
||||
static inline void pre_console_putc(const char c) {}
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ config SPL_AHCI_PCI
|
|||
bool "Support for PCI-based AHCI controller for SPL"
|
||||
depends on SPL
|
||||
depends on SPL_PCI
|
||||
depends on SPL_SATA_SUPPORT && DM_SCSI
|
||||
depends on SPL_SATA && DM_SCSI
|
||||
|
||||
config DWC_AHCI
|
||||
bool "Enable Synopsys DWC AHCI driver support"
|
||||
|
|
|
|||
|
|
@ -115,10 +115,14 @@ struct global_data {
|
|||
/**
|
||||
* @precon_buf_idx: pre-console buffer index
|
||||
*
|
||||
* @precon_buf_idx indicates the current position of the buffer used to
|
||||
* collect output before the console becomes available
|
||||
* @precon_buf_idx indicates the current position of the
|
||||
* buffer used to collect output before the console becomes
|
||||
* available. When negative, the pre-console buffer is
|
||||
* temporarily disabled (used when the pre-console buffer is
|
||||
* being written out, to prevent adding its contents to
|
||||
* itself).
|
||||
*/
|
||||
unsigned long precon_buf_idx;
|
||||
long precon_buf_idx;
|
||||
#endif
|
||||
/**
|
||||
* @env_addr: address of environment structure
|
||||
|
|
|
|||
|
|
@ -1,369 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2009-2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2020-2021 NXP
|
||||
*/
|
||||
|
||||
/*
|
||||
* Corenet DS style board configuration file
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include "../board/freescale/common/ics307_clk.h"
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
/* Set 1M boot space */
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
|
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
|
||||
#endif
|
||||
#define CONFIG_SYS_L3_SIZE (1024 << 10)
|
||||
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
#define SPD_EEPROM_ADDRESS2 0x52
|
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
|
||||
/* Set the local bus clock 1/8 of platform clock */
|
||||
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define PIXIS_BASE_PHYS 0xfffdf0000ull
|
||||
#else
|
||||
#define PIXIS_BASE_PHYS PIXIS_BASE
|
||||
#endif
|
||||
|
||||
#define PIXIS_LBMAP_SWITCH 7
|
||||
#define PIXIS_LBMAP_MASK 0xf0
|
||||
#define PIXIS_LBMAP_SHIFT 4
|
||||
#define PIXIS_LBMAP_ALTBANK 0x40
|
||||
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
/* Nand Flash */
|
||||
#ifdef CONFIG_NAND_FSL_ELBC
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#endif /* CONFIG_NAND_FSL_ELBC */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
|
||||
/* I2C */
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
*/
|
||||
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
||||
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
||||
/*
|
||||
* for slave u-boot IMAGE instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
|
||||
/*
|
||||
* for slave UCODE and ENV instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
|
||||
|
||||
/* slave core release by master*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
|
||||
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
|
||||
|
||||
/*
|
||||
* SRIO_PCIE_BOOT - SLAVE
|
||||
*/
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
|
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
|
||||
/* controller 4, Base address 203000 */
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
|
||||
/* Qman/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
|
||||
#else
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
|
||||
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
|
||||
|
||||
#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
|
||||
#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
|
||||
|
||||
#define CONFIG_SYS_TBIPA_VALUE 8
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#ifdef CONFIG_TARGET_P4080DS
|
||||
#define __USB_PHY_TYPE ulpi
|
||||
#else
|
||||
#define __USB_PHY_TYPE utmi
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
|
||||
"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=p4080ds/p4080ds.dtb\0" \
|
||||
"bdev=sda3\0"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -46,7 +46,7 @@ int do_fat_fsload(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||
int do_ext2load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
|
||||
|
||||
/*
|
||||
* Tell the fs layer which block device an partition to use for future
|
||||
* Tell the fs layer which block device and partition to use for future
|
||||
* commands. This also internally identifies the filesystem that is present
|
||||
* within the partition. The identification process may be limited to a
|
||||
* specific filesystem type by passing FS_* in the fstype parameter.
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ hostcxx_flags = -Wp,-MD,$(depfile) $(__hostcxx_flags)
|
|||
# Create executable from a single .c file
|
||||
# host-csingle -> Executable
|
||||
quiet_cmd_host-csingle = HOSTCC $@
|
||||
cmd_host-csingle = $(HOSTCC) $(hostc_flags) -o $@ $< \
|
||||
cmd_host-csingle = $(HOSTCC) $(hostc_flags) $(KBUILD_HOSTLDFLAGS) -o $@ $< \
|
||||
$(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
|
||||
$(host-csingle): $(obj)/%: $(src)/%.c FORCE
|
||||
$(call if_changed_dep,host-csingle)
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#define pr_warn(fmt, args...) fprintf(stderr, pr_fmt(fmt), "warning", ##args)
|
||||
#define pr_info(fmt, args...) fprintf(stderr, pr_fmt(fmt), "info", ##args)
|
||||
|
||||
#if defined(LIBRESSL_VERSION_NUMBER)
|
||||
#if defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x3050000fL
|
||||
#define RSA_get0_n(key) (key)->n
|
||||
#define RSA_get0_e(key) (key)->e
|
||||
#define RSA_get0_d(key) (key)->d
|
||||
|
|
|
|||
Loading…
Reference in New Issue