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imx8mn: synchronise device tree with linux 

Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:43:37 +02:00 committed by Stefano Babic
parent a68bad0a37
commit 4e5114daf9
15 changed files with 608 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/imx8mn-beacon-baseboard.dtsi
View File

@ -126,7 +126,6 @@
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "xclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
@ -176,6 +175,7 @@
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
@ -259,6 +259,8 @@
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};

12
arch/arm/dts/imx8mn-beacon-som.dtsi
View File

@ -101,7 +101,7 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
@ -120,6 +120,9 @@
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
@ -262,12 +265,15 @@
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&buck4_reg>;
vqmmc-supply = <&buck5_reg>;
bus-width = <4>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";

115
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
View File

@ -4,6 +4,8 @@
* Copyright 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include "imx8mn.dtsi"
/ {
@ -11,17 +13,17 @@
stdout-path = &uart4;
};
fec_supply: fec_supply_en {
fec_supply: fec-supply-en {
compatible = "regulator-fixed";
vin-supply = <&buck4_reg>;
regulator-name = "tja1101_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vin-supply = <&buck4_reg>;
enable-active-high;
};
usdhc2_pwrseq: usdhc2_pwrseq {
usdhc2_pwrseq: usdhc2-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
@ -57,8 +59,6 @@
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&fec_supply>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
fsl,magic-packet;
status = "okay";
@ -69,6 +69,9 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <2000>;
};
};
};
@ -280,6 +283,14 @@
};
&iomuxc {
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
>;
};
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
@ -289,6 +300,26 @@
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
@ -316,6 +347,22 @@
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
@ -323,12 +370,6 @@
>;
};
pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
@ -362,36 +403,9 @@
>;
};
pinctrl_wlan: wlangrp {
pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
>;
};
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
>;
};
@ -401,23 +415,12 @@
>;
};
pinctrl_fec1: fec1grp {
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
>;
};
};

90
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
#include <dt-bindings/sound/tlv320aic31xx.h>
/ {
model = "BSH SMM S2 PRO";
@ -16,6 +17,65 @@
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};
sound-tlv320aic31xx {
compatible = "fsl,imx-audio-tlv320aic31xx";
model = "tlv320aic31xx-hifi";
audio-cpu = <&sai3>;
audio-codec = <&tlv320dac3101>;
audio-asrc = <&easrc>;
audio-routing =
"Ext Spk", "SPL",
"Ext Spk", "SPR";
mclk-id = <PLL_CLKIN_BCLK>;
};
vdd_input: vdd_input {
compatible = "regulator-fixed";
regulator-name = "vdd_input";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-format = <10>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tlv320dac3101: audio-codec@18 {
compatible = "ti,tlv320dac3101";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dac_rst>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&buck4_reg>;
SPRVDD-supply = <&vdd_input>;
SPLVDD-supply = <&vdd_input>;
AVDD-supply = <&buck4_reg>;
IOVDD-supply = <&buck4_reg>;
DVDD-supply = <&buck5_reg>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
ai31xx-micbias-vg = <MICBIAS_AVDDV>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
@ -30,6 +90,36 @@
};
&iomuxc {
pinctrl_dac_rst: dacrstgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
>;
};
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090

4
arch/arm/dts/imx8mn-ddr4-evk.dts
View File

@ -59,6 +59,10 @@
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";

4
arch/arm/dts/imx8mn-evk-u-boot.dtsi
View File

@ -9,11 +9,11 @@
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};

56
arch/arm/dts/imx8mn-evk.dts
View File

@ -31,7 +31,7 @@
};
&i2c1 {
pmic: pca9450@25 {
pmic: pmic@25 {
compatible = "nxp,pca9450b";
reg = <0x25>;
pinctrl-names = "default";
@ -41,18 +41,18 @@
regulators {
buck1: BUCK1{
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-name = "VDD_SOC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-name = "VDD_ARM_0V9";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
@ -61,63 +61,63 @@
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-name = "NVCC_DRAM_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-name = "NVCC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-name = "VDD_SNVS_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDD_PHY_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;

121
arch/arm/dts/imx8mn-evk.dtsi
View File

@ -46,6 +46,40 @@
pinctrl-0 = <&pinctrl_ir>;
linux,autosuspend-period = <125>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_wlf>;
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "mclk";
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8524>;
audio-asrc = <&easrc>;
audio-routing =
"Line Out Jack", "LINEVOUTL",
"Line Out Jack", "LINEVOUTR";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&fec1 {
@ -76,6 +110,22 @@
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <166000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -133,22 +183,51 @@
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
@ -213,12 +292,29 @@
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_gpio_wlf: gpiowlfgrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
pinctrl_ir: irgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
@ -258,6 +354,22 @@
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
@ -271,6 +383,15 @@
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4

15
arch/arm/dts/imx8mn-var-som.dtsi
View File

@ -70,12 +70,12 @@
pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
touchscreen-size-x = /bits/ 16 <4008>;
touchscreen-size-x = <4008>;
ti,y-min = /bits/ 16 <282>;
touchscreen-size-y = /bits/ 16 <3864>;
touchscreen-size-y = <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
touchscreen-max-pressure = /bits/ 16 <255>;
touchscreen-average-samples = /bits/ 16 <10>;
touchscreen-max-pressure = <255>;
touchscreen-average-samples = <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
@ -91,8 +91,6 @@
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
@ -103,6 +101,8 @@
ethphy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
@ -260,7 +260,8 @@
};
&usbotg1 {
dr_mode = "peripheral";
dr_mode = "otg";
usb-role-switch;
status = "okay";
};

80
arch/arm/dts/imx8mn-venice-gw7902.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Gateworks Corporation
* Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
@ -140,12 +140,13 @@
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1>;
compatible = "regulator-fixed";
regulator-name = "usb_usb1_vbus";
gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
@ -154,9 +155,9 @@
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl>;
compatible = "regulator-fixed";
regulator-name = "wifi";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
@ -219,6 +220,10 @@
};
};
&disp_blk_ctrl {
status = "disabled";
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
@ -242,18 +247,55 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/* TI DP83867 props */
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
/* GPY111 props */
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2500>;
};
};
};
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names = "", "", "", "", "", "", "", "",
"uart2_en#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "app_gpio1", "", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
&gpio5 {
gpio-line-names = "", "", "", "mipi_gpio4",
"mipi_gpio3", "mipi_gpio2", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpu {
status = "disabled";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -529,20 +571,15 @@
status = "okay";
accelerometer@19 {
compatible = "st,lis2de12";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
secure-element@60 {
compatible = "nxp,se050";
reg = <0x60>;
};
};
/* off-board header */
@ -561,6 +598,10 @@
status = "okay";
};
&pgc_gpumix {
status = "disabled";
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
@ -591,6 +632,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {
@ -648,7 +690,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
@ -726,11 +768,11 @@
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};

270
arch/arm/dts/imx8mn.dtsi
View File

@ -65,6 +65,12 @@
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
nvmem-cells = <&cpu_speed_grade>;
@ -80,6 +86,12 @@
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
@ -93,6 +105,12 @@
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
@ -106,6 +124,12 @@
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
@ -114,6 +138,10 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
@ -192,7 +220,6 @@
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
psci {
@ -247,6 +274,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
@ -257,7 +285,7 @@
#size-cells = <1>;
ranges;
spba: spba-bus@30000000 {
spba2: spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -265,7 +293,7 @@
ranges;
sai2: sai@30020000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
@ -279,7 +307,7 @@
};
sai3: sai@30030000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
@ -293,7 +321,7 @@
};
sai5: sai@30050000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
@ -309,7 +337,7 @@
};
sai6: sai@30060000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
@ -366,7 +394,7 @@
};
sai7: sai@300b0000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
@ -641,24 +669,23 @@
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
<&clk IMX8MN_CLK_GPU_SHADER_DIV>,
<&clk IMX8MN_CLK_GPU_SHADER>,
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
<&clk IMX8MN_CLK_GPU_AHB>;
resets = <&src IMX8MQ_RESET_GPU_RESET>;
};
dispmix_pd: power-domain@3 {
pgc_dispmix: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
};
mipi_pd: power-domain@4 {
pgc_mipi: power-domain@4 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_MIPI>;
power-domains = <&dispmix_pd>;
power-domains = <&pgc_dispmix>;
};
};
};
@ -678,7 +705,7 @@
clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
<&clk IMX8MN_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -689,7 +716,7 @@
clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
<&clk IMX8MN_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -700,7 +727,7 @@
clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
<&clk IMX8MN_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -711,7 +738,7 @@
clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
<&clk IMX8MN_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -731,80 +758,88 @@
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
spba1: spba-bus@30800000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
<&clk IMX8MN_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
#size-cells = <1>;
reg = <0x30800000 0x100000>;
ranges;
ecspi2: spi@30830000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
<&clk IMX8MN_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi1: spi@30820000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
<&clk IMX8MN_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
<&clk IMX8MN_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
<&clk IMX8MN_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
<&clk IMX8MN_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
<&clk IMX8MN_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
<&clk IMX8MN_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
<&clk IMX8MN_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
<&clk IMX8MN_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
uart3: serial@30880000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
<&clk IMX8MN_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
<&clk IMX8MN_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
};
};
crypto: crypto@30900000 {
@ -898,7 +933,7 @@
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
@ -912,7 +947,7 @@
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
@ -926,7 +961,7 @@
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
@ -948,7 +983,7 @@
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
<&clk IMX8MN_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
clock-names = "fspi_en", "fspi";
status = "disabled";
};
@ -964,7 +999,7 @@
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
@ -990,7 +1025,6 @@
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
@ -1004,6 +1038,34 @@
#size-cells = <1>;
ranges;
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
<&pgc_dispmix>, <&pgc_mipi>,
<&pgc_mipi>;
power-domain-names = "bus", "isi",
"lcdif", "mipi-dsi",
"mipi-csi";
clocks = <&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
<&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
clock-names = "disp_axi", "disp_apb",
"disp_axi_root", "disp_apb_root",
"lcdif-axi", "lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk";
#power-domain-cells = <1>;
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
@ -1054,6 +1116,32 @@
status = "disabled";
};
gpu: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPU_AHB>,
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
<&clk IMX8MN_CLK_GPU_SHADER>;
clock-names = "reg", "bus", "core", "shader";
assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
<&clk IMX8MN_CLK_GPU_SHADER>,
<&clk IMX8MN_CLK_GPU_AXI>,
<&clk IMX8MN_CLK_GPU_AHB>,
<&clk IMX8MN_GPU_PLL>;
assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
<&clk IMX8MN_GPU_PLL_OUT>,
<&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
<400000000>,
<800000000>,
<400000000>,
<1200000000>;
power-domains = <&pgc_gpumix>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,

2
board/freescale/imx8mn_evk/spl.c
View File

@ -69,7 +69,7 @@ int power_init_board(void)
struct udevice *dev;
int ret;
ret = pmic_get("pca9450@25", &dev);
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("No pca9450@25\n");
return 0;

25
include/dt-bindings/clock/imx8mn-clock.h
View File

@ -234,6 +234,29 @@
#define IMX8MN_CLK_A53_CORE 214
#define IMX8MN_CLK_END 215
#define IMX8MN_CLK_CLKOUT1_SEL 215
#define IMX8MN_CLK_CLKOUT1_DIV 216
#define IMX8MN_CLK_CLKOUT1 217
#define IMX8MN_CLK_CLKOUT2_SEL 218
#define IMX8MN_CLK_CLKOUT2_DIV 219
#define IMX8MN_CLK_CLKOUT2 220
#define IMX8MN_CLK_M7_CORE 221
#define IMX8MN_CLK_GPT_3M 222
#define IMX8MN_CLK_GPT1 223
#define IMX8MN_CLK_GPT1_ROOT 224
#define IMX8MN_CLK_GPT2 225
#define IMX8MN_CLK_GPT2_ROOT 226
#define IMX8MN_CLK_GPT3 227
#define IMX8MN_CLK_GPT3_ROOT 228
#define IMX8MN_CLK_GPT4 229
#define IMX8MN_CLK_GPT4_ROOT 230
#define IMX8MN_CLK_GPT5 231
#define IMX8MN_CLK_GPT5_ROOT 232
#define IMX8MN_CLK_GPT6 233
#define IMX8MN_CLK_GPT6_ROOT 234
#define IMX8MN_CLK_END 235
#endif

5
include/dt-bindings/power/imx8mn-power.h
View File

@ -12,4 +12,9 @@
#define IMX8MN_POWER_DOMAIN_DISPMIX 3
#define IMX8MN_POWER_DOMAIN_MIPI 4
#define IMX8MN_DISPBLK_PD_MIPI_DSI 0
#define IMX8MN_DISPBLK_PD_MIPI_CSI 1
#define IMX8MN_DISPBLK_PD_LCDIF 2
#define IMX8MN_DISPBLK_PD_ISI 3
#endif

14
include/dt-bindings/sound/tlv320aic31xx.h Normal file
View File

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_TLV320AIC31XX_H
#define __DT_TLV320AIC31XX_H
#define MICBIAS_2_0V 1
#define MICBIAS_2_5V 2
#define MICBIAS_AVDDV 3
#define PLL_CLKIN_MCLK 0x00
#define PLL_CLKIN_BCLK 0x01
#define PLL_CLKIN_GPIO1 0x02
#define PLL_CLKIN_DIN 0x03
#endif /* __DT_TLV320AIC31XX_H */