arm: dts: add am62p5 dtbs from linux
Pull in the device tree source files for TI's am62p5 SoCs needed to boot the board from v6.6-rc5. These are an early release with only the peripherals to boot the board via UART boot [bb@ti.com: used DTBs from TI's v6.1 kernel] Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
Praneeth Bajjuri
parent
9fa86d1770
commit
5014368187
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@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P main domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x70000000 0x10000>;
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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dmss: bus@48000000 {
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bootph-all;
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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bootph-all;
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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dmsc: system-controller@44043000 {
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bootph-all;
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes = <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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k3_pds: power-controller {
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bootph-all;
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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bootph-all;
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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bootph-all;
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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bootph-all;
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2ac>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_timer0: timer@2400000 {
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bootph-all;
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compatible = "ti,am654-timer";
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reg = <0x00 0x2400000 0x00 0x400>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 36 2>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 36 2>;
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assigned-clock-parents = <&k3_clks 36 3>;
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power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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};
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@ -0,0 +1,15 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P MCU domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_pmx0: pinctrl@4084000 {
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compatible = "pinctrl-single";
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reg = <0x00 0x04084000 0x00 0x88>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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};
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P wakeup domain peripherals
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_wakeup {
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wkup_conf: bus@43000000 {
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bootph-all;
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compatible = "simple-bus";
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reg = <0x00 0x43000000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x43000000 0x20000>;
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chipid: chipid@14 {
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bootph-all;
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compatible = "ti,am654-chipid";
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reg = <0x14 0x4>;
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};
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};
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wkup_uart0: serial@2b300000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x2b300000 0x00 0x100>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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};
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@ -0,0 +1,122 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM62P SoC Family
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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model = "Texas Instruments K3 AM62P5 SoC";
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compatible = "ti,am62p5";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f0000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
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<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
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<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
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<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
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<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
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<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
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<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
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<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
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<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
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<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
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<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
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<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
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<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
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<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
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<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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/* MCU Domain Range */
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<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
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<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
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<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
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<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
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<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
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/* Wakeup Domain Range */
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<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
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<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
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<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
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cbass_mcu: bus@4000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
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<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
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<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
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<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
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<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
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};
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cbass_wakeup: bus@b00000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
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<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
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<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
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};
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};
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};
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/* Now include peripherals for each bus segment */
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#include "k3-am62p-main.dtsi"
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#include "k3-am62p-mcu.dtsi"
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#include "k3-am62p-wakeup.dtsi"
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@ -0,0 +1,116 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree file for the AM62P5-SK
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Schematics: https://www.ti.com/lit/zip/sprr487
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*/
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/dts-v1/;
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#include "k3-am62p5.dtsi"
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/ {
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compatible = "ti,am62p5-sk", "ti,am62p5";
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model = "Texas Instruments AM62P5 SK";
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aliases {
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serial0 = &wkup_uart0;
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serial2 = &main_uart0;
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serial3 = &main_uart1;
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};
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chosen {
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stdout-path = &main_uart0;
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};
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memory@80000000 {
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/* 8G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000001 0x80000000>;
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_tfa_ddr: tfa@9e780000 {
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reg = <0x00 0x9e780000 0x00 0x80000>;
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no-map;
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};
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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no-map;
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};
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wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9c900000 0x00 0x01e00000>;
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no-map;
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};
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};
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};
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&main_pmx0 {
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main_uart0_pins_default: main-uart0-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
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AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
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AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */
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AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */
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>;
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};
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main_uart1_pins_default: main-uart1-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */
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AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */
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AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */
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AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */
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>;
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};
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};
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&main_uart0 {
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bootph-all;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&main_uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart1_pins_default>;
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/* Main UART1 is used by TIFS firmware */
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status = "reserved";
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};
|
||||
|
||||
&cbass_mcu {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
bootph-all;
|
||||
wkup_uart0_pins_default: wkup-uart0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
|
||||
AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
|
||||
AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
|
||||
AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
bootph-all;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
status = "reserved";
|
||||
};
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree file for the AM62P5 SoC family (quad core)
|
||||
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruj83
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62p.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 136 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 137 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 138 0>;
|
||||
};
|
||||
};
|
||||
|
||||
l2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants for pinctrl bindings for TI's K3 SoC
|
||||
* family.
|
||||
*
|
||||
* Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#ifndef DTS_ARM64_TI_K3_PINCTRL_H
|
||||
#define DTS_ARM64_TI_K3_PINCTRL_H
|
||||
|
||||
#define PULLUDEN_SHIFT (16)
|
||||
#define PULLTYPESEL_SHIFT (17)
|
||||
#define RXACTIVE_SHIFT (18)
|
||||
#define DEBOUNCE_SHIFT (11)
|
||||
|
||||
#define PULL_DISABLE (1 << PULLUDEN_SHIFT)
|
||||
#define PULL_ENABLE (0 << PULLUDEN_SHIFT)
|
||||
|
||||
#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE)
|
||||
#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
|
||||
|
||||
#define INPUT_EN (1 << RXACTIVE_SHIFT)
|
||||
#define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
|
||||
|
||||
/* Only these macros are expected be used directly in device tree files */
|
||||
#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE)
|
||||
#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP)
|
||||
#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN)
|
||||
#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
|
||||
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN)
|
||||
|
||||
#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
|
||||
|
||||
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue