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arm: cp15: update DACR value to activate access control 

Update the initial value of Domain Access Control Register (DACR)
and set by default the access permission to client (DACR_Dn_CLIENT = 1U)
for each of the 16 domains and no more to all-supervisor
(DACR_Dn_MANAGER = 3U).

This patch allows to activate the domain checking in MMU against the
permission bits in the translation tables and avoids prefetching issue
on ARMv7 [1].

Today it was already done for OMAP2 architecture
./arch/arm/mach-omap2/omap-cache.c::arm_init_domains
introduced by commit de63ac278c ("ARM: mmu: Set domain permissions
to client access") which fixes lot of speculative prefetch aborts seen
on OMAP5 secure devices.

[1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Patrick Delaunay 2021-02-05 13:53:36 +01:00 committed by Tom Rini
parent 9b39d249e0
commit 503eea4519
1 changed files with 5 additions and 2 deletions
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7
arch/arm/lib/cache-cp15.c
View File

@ -203,9 +203,12 @@ static inline void mmu_setup(void)
asm volatile("mcr p15, 0, %0, c2, c0, 0" asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (gd->arch.tlb_addr) : "memory"); : : "r" (gd->arch.tlb_addr) : "memory");
#endif #endif
/* Set the access control to all-supervisor */ /*
* initial value of Domain Access Control Register (DACR)
* Set the access control to client (1U) for each of the 16 domains
*/
asm volatile("mcr p15, 0, %0, c3, c0, 0" asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0)); : : "r" (0x55555555));
arm_init_domains(); arm_init_domains();