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nmhw23: refactor device tree 

Apply the same style as in kernel
device tree: alphabetic order, etc.
This commit is contained in:
Andrejs Cainikovs 2019-08-28 14:28:42 +02:00
parent 4ea2816a36
commit 5212243198
1 changed files with 65 additions and 66 deletions
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131
arch/arm/dts/imx8_nmhw23.dts
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@ -57,7 +57,6 @@
gpio-reset-sw = <&gpio0 5 GPIO_ACTIVE_LOW>;
};
};
};
&iomuxc {
@ -65,6 +64,22 @@
pinctrl-0 = <&pinctrl_hog>;
imx8-nmhw23 {
pinctrl_eth: eth_grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000060
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000060
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN 0x06000060
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x06000040
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
@ -78,6 +93,33 @@
>;
};
pinctrl_reset_hsm: reset_hsm_grp {
fsl,pins = <
SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000060
>;
};
pinctrl_reset_phy: reset_phy_grp {
fsl,pins = <
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000021
>;
};
pinctrl_reset_sw: reset_sw_grp {
fsl,pins = <
SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 0x00000060
>;
};
pinctrl_spi3: spi3_grp {
fsl,pins = <
SC_P_SPI3_SCK_LSIO_GPIO0_IO13 0x00000041
SC_P_SPI3_SDO_LSIO_GPIO0_IO14 0x00000041
SC_P_SPI3_SDI_LSIO_GPIO0_IO15 0x00000041
SC_P_SPI3_CS0_LSIO_GPIO0_IO16 0x00000061
>;
};
pinctrl_usdhc1: usdhc1_grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
@ -125,74 +167,9 @@
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
>;
};
pinctrl_spi3: spi3_grp {
fsl,pins = <
SC_P_SPI3_SCK_LSIO_GPIO0_IO13 0x00000041
SC_P_SPI3_SDO_LSIO_GPIO0_IO14 0x00000041
SC_P_SPI3_SDI_LSIO_GPIO0_IO15 0x00000041
SC_P_SPI3_CS0_LSIO_GPIO0_IO16 0x00000061
>;
};
pinctrl_reset_hsm: reset_hsm_grp {
fsl,pins = <
SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000060
>;
};
pinctrl_reset_phy: reset_phy_grp {
fsl,pins = <
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000021
>;
};
pinctrl_reset_sw: reset_sw_grp {
fsl,pins = <
SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 0x00000060
>;
};
pinctrl_eth: eth_grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000060
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000060
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN 0x06000060
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x06000040
>;
};
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
@ -220,6 +197,28 @@
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;