- CFG_RX_ETH_BUFFER added.
This commit is contained in:
stroese
parent
c602883592
commit
53cf9435cc
10
README
10
README
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@ -690,7 +690,7 @@ The following options need to be configured:
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- NETWORK Support (PCI):
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CONFIG_E1000
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Support for Intel 8254x gigabit chips.
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CONFIG_EEPRO100
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Support for Intel 82557/82559/82559ER chips.
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Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
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@ -1442,6 +1442,14 @@ Configuration Settings:
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Define if the flash driver uses extra elements in the
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common flash structure for storing flash geometry
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- CFG_RX_ETH_BUFFER:
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Defines the number of ethernet receive buffers. On some
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ethernet controllers it is recommended to set this value
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to 8 or even higher (EEPRO100 or 405 EMAC), since all
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buffers can be full shortly after enabling the interface
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on high ethernet traffic.
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Defaults to 4 if not defined.
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The following definitions that deal with the placement and management
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of environment data (variable area); in general, we support the
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following configurations:
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@ -125,6 +125,10 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------
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@ -144,7 +144,7 @@
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/*
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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@ -171,7 +171,7 @@
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* Memory configuration using SPD information stored on the SODIMMs
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* not yet supported.
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*/
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#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
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/* Bit-field values for MCCR1.
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@ -186,7 +186,7 @@
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#else
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# error "SDRAM size not supported"
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#endif
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#define CFG_BANK1_ROW 0
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#define CFG_BANK1_ROW 0
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#define CFG_BANK2_ROW 0
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#define CFG_BANK3_ROW 0
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#define CFG_BANK4_ROW 0
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@ -361,7 +361,7 @@
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/* IRQ_ENA_2 bit definitions */
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#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
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#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
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#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
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#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
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#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
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#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
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#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
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@ -371,9 +371,9 @@
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/* IRQ_STAT_2 bit definitions */
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#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
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#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
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#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
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#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
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#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
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#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
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#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
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#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
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#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
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#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
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@ -421,14 +421,14 @@
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#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
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#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
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#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
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#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
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#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
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#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
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#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
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#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
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#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
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#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
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#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
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#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
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#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
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#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
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#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
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#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
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/*-----------------------------------------------------------------------
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@ -441,6 +441,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x00104000
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#define PCI_ENET0_MEMADDR 0x82000000
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@ -146,6 +146,8 @@
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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@ -55,15 +55,7 @@
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#endif
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#undef CONFIG_BOOTARGS
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm ffc00000 ffca0000"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm ffc00000"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#define CONFIG_BOOTCOMMAND "bootm 100000" /* default boot command */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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@ -73,12 +65,7 @@
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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#if 0 /* test-only */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_VENDOREX)
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#else
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT)
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#endif
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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@ -147,6 +134,8 @@
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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@ -202,7 +191,7 @@
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#define CFG_FLASH_BASE 0xFFFC0000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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@ -360,7 +349,7 @@
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#define CFG_FPGA_STATUS_TS_IRQ 0x1000
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_MAX_SIZE 64*1024 /* 64kByte is enough for XC2S15 */
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#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */
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/* FPGA program pin configuration */
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#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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@ -304,6 +304,7 @@
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#define CFG_ETH_IOBASE 0x00104000
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x00104000
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#define PCI_ENET0_MEMADDR 0x80000000
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#endif /* __CONFIG_H */
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@ -333,6 +333,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_EEPRO100_SROM_WRITE
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#endif /* __CONFIG_H */
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@ -94,6 +94,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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@ -261,6 +261,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_TULIP
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#endif /* __CONFIG_H */
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@ -263,6 +263,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_TULIP
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@ -316,6 +316,7 @@
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#endif
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/*
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@ -128,6 +128,10 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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@ -82,6 +82,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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@ -81,6 +81,7 @@
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_NATSEMI
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#define CONFIG_NS8382X
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#define CONFIG_X86 1 /* This is a X86 CPU */
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#define CONFIG_SC520 1 /* Include support for AMD SC520 */
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#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
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#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
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#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
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#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
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@ -71,7 +71,7 @@
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#define CONFIG_BOOTDELAY 15
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#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
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#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
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#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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@ -123,7 +123,7 @@
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#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
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#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
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#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@ -131,7 +131,7 @@
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#if 0
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/* Environment in flash */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */
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# define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */
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# define CFG_ENV_OFFSET 0
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@ -143,7 +143,7 @@
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# define CONFIG_SPI
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# define CONFIG_SPI_X 1
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# define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */
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# define CFG_ENV_OFFSET 0x1c00
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# define CFG_ENV_OFFSET 0x1c00
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#endif
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@ -155,6 +155,7 @@
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*/
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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/************************************************************
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* IDE/ATA stuff
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@ -204,8 +205,8 @@
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#define CONFIG_PCI_SCAN_SHOW
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#define CFG_FIRST_PCI_IRQ 9
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#define CFG_SECOND_PCI_IRQ 10
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#define CFG_THIRD_PCI_IRQ 11
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#define CFG_SECOND_PCI_IRQ 10
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#define CFG_THIRD_PCI_IRQ 11
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#define CFG_FORTH_PCI_IRQ 12
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@ -125,6 +125,7 @@ protect on $(u-boot_startaddr) $(u-boot_endaddr)"
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_NET_MULTI
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_EEPRO100_SROM_WRITE
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#define PCI_ENET0_IOADDR 0xF0000000
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