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sh: rsk7269: Remove the board 

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut 2019-05-07 21:51:39 +02:00 committed by Marek Vasut
parent 58300f399f
commit 54eac8b3a3
8 changed files with 0 additions and 337 deletions
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5
arch/sh/Kconfig
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@ -31,10 +31,6 @@ choice
prompt "Target select" prompt "Target select"
optional optional
config TARGET_RSK7269
bool "RSK2+SH7269"
select CPU_SH2A
config TARGET_MPR2 config TARGET_MPR2
bool "Magic Panel Release 2 board" bool "Magic Panel Release 2 board"
select CPU_SH3 select CPU_SH3
@ -122,7 +118,6 @@ source "board/renesas/ap325rxa/Kconfig"
source "board/renesas/r0p7734/Kconfig" source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig" source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig" source "board/renesas/r7780mp/Kconfig"
source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig" source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7757lcr/Kconfig"

12
board/renesas/rsk7269/Kconfig
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@ -1,12 +0,0 @@
if TARGET_RSK7269
config SYS_BOARD
default "rsk7269"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "rsk7269"
endif

6
board/renesas/rsk7269/MAINTAINERS
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@ -1,6 +0,0 @@
RSK7269 BOARD
#M: -
S: Maintained
F: board/renesas/rsk7269/
F: include/configs/rsk7269.h
F: configs/rsk7269_defconfig

8
board/renesas/rsk7269/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012 Renesas Electronics Europe Ltd.
# Copyright (C) 2012 Phil Edworthy
#
obj-y := rsk7269.o
extra-y += lowlevel_init.o

179
board/renesas/rsk7269/lowlevel_init.S
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@ -1,179 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Renesas Electronics Europe Ltd.
* Copyright (C) 2012 Phil Edworthy
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2008 Nobuhiro Iwamatsu
*
* Based on board/renesas/rsk7264/lowlevel_init.S
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
/* Flush and enable caches (data cache in write-through mode) */
write32 CCR1_A ,CCR1_D
/* Disable WDT */
write16 WTCSR_A, WTCSR_D
write16 WTCNT_A, WTCNT_D
/* Disable Register Bank interrupts */
write16 IBNR_A, IBNR_D
/* Set clocks based on 13.225MHz xtal */
write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
/* Enable all peripherals */
write8 STBCR3_A, STBCR3_D
write8 STBCR4_A, STBCR4_D
write8 STBCR5_A, STBCR5_D
write8 STBCR6_A, STBCR6_D
write8 STBCR7_A, STBCR7_D
write8 STBCR8_A, STBCR8_D
write8 STBCR9_A, STBCR9_D
write8 STBCR10_A, STBCR10_D
/* SCIF7 and IIC2 */
write16 PJCR3_A, PJCR3_D /* TXD7 */
write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
/* Configure bus (CS0) */
write16 PFCR3_A, PFCR3_D /* A24 */
write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
write32 CS0WCR_A, CS0WCR_D
write32 CS0BCR_A, CS0BCR_D
/* Configure SDRAM (CS3) */
write16 PCCR2_A, PCCR2_D /* CS3# */
write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
write32 CS3BCR_A, CS3BCR_D
write32 CS3WCR_A, CS3WCR_D
write32 SDCR_A, SDCR_D
write32 RTCOR_A, RTCOR_D
write32 RTCSR_A, RTCSR_D
/* Configure ethernet (CS1) */
write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
write16 PHCR0_A, PHCR0_D
write16 PFCR2_A, PFCR2_D /* CS1# */
write32 CS1BCR_A, CS1BCR_D /* Big endian */
write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
write16 PJIOR1_A, PJIOR1_D
/* wait 200us */
mov.l REPEAT_D, r3
mov #0, r2
repeat0:
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
mov.l SDRAM_MODE, r1
mov #0, r0
mov.l r0, @r1
nop
rts
.align 4
CCR1_A: .long CCR1
CCR1_D: .long 0x0000090B
STBCR3_A: .long 0xFFFE0408
STBCR4_A: .long 0xFFFE040C
STBCR5_A: .long 0xFFFE0410
STBCR6_A: .long 0xFFFE0414
STBCR7_A: .long 0xFFFE0418
STBCR8_A: .long 0xFFFE041C
STBCR9_A: .long 0xFFFE0440
STBCR10_A: .long 0xFFFE0444
STBCR3_D: .long 0x0000001A
STBCR4_D: .long 0x00000000
STBCR5_D: .long 0x00000000
STBCR6_D: .long 0x00000000
STBCR7_D: .long 0x00000012
STBCR8_D: .long 0x00000009
STBCR9_D: .long 0x00000000
STBCR10_D: .long 0x00000010
WTCSR_A: .long 0xFFFE0000
WTCNT_A: .long 0xFFFE0002
WTCSR_D: .word 0xA518
WTCNT_D: .word 0x5A00
IBNR_A: .long 0xFFFE080E
IBNR_D: .word 0x0000
.align 2
FRQCR_A: .long 0xFFFE0010
FRQCR_D: .word 0x0015
.align 2
PJCR3_A: .long 0xFFFE3908
PJCR3_D: .word 0x5000
.align 2
PECR1_A: .long 0xFFFE388C
PECR1_D: .word 0x2011
.align 2
PFCR3_A: .long 0xFFFE38A8
PFCR2_A: .long 0xFFFE38AA
PBCR5_A: .long 0xFFFE3824
PFCR3_D: .word 0x0010
PFCR2_D: .word 0x0101
PBCR5_D: .word 0x0111
.align 2
CS0WCR_A: .long 0xFFFC0028
CS0WCR_D: .long 0x00000341
CS0BCR_A: .long 0xFFFC0004
CS0BCR_D: .long 0x00000400
PCCR2_A: .long 0xFFFE384A
PCCR1_A: .long 0xFFFE384C
PCCR0_A: .long 0xFFFE384E
PCCR2_D: .word 0x0001
PCCR1_D: .word 0x1111
PCCR0_D: .word 0x1111
.align 2
CS3BCR_A: .long 0xFFFC0010
CS3BCR_D: .long 0x00004400
CS3WCR_A: .long 0xFFFC0034
CS3WCR_D: .long 0x00004912
SDCR_A: .long 0xFFFC004C
SDCR_D: .long 0x00000811
RTCOR_A: .long 0xFFFC0058
RTCOR_D: .long 0xA55A0035
RTCSR_A: .long 0xFFFC0050
RTCSR_D: .long 0xA55A0010
.align 2
SDRAM_MODE: .long 0xFFFC5460
REPEAT_D: .long 0x000033F1
PHCR1_A: .long 0xFFFE38EC
PHCR0_A: .long 0xFFFE38EE
PHCR1_D: .word 0x2222
PHCR0_D: .word 0x2222
.align 2
CS1BCR_A: .long 0xFFFC0008
CS1BCR_D: .long 0x00000400
CS1WCR_A: .long 0xFFFC002C
CS1WCR_D: .long 0x00000080
PJDR1_A: .long 0xFFFE3914
PJDR1_D: .word 0x0000
.align 2
PJIOR1_A: .long 0xFFFE3910
PJIOR1_D: .word 0x8000
.align 2

61
board/renesas/rsk7269/rsk7269.c
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@ -1,61 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Renesas Electronics Europe Ltd.
* Copyright (C) 2012 Phil Edworthy
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2008 Nobuhiro Iwamatsu
*
* Based on u-boot/board/rsk7264/rsk7264.c
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("BOARD: Renesas RSK7269\n");
return 0;
}
int board_init(void)
{
return 0;
}
void led_set_state(unsigned short value)
{
}
/*
* The RSK board has the SMSC89218 wired up 'incorrectly'.
* Byte-swapping is necessary, and so poor performance is inevitable.
* This problem cannot evade by the swap function of CHIP, this can
* evade by software Byte-swapping.
* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
* functions necessary to solve this problem.
*/
u32 pkt_data_pull(struct eth_device *dev, u32 addr)
{
volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
| swab16(*(addr_16 + 1));
}
void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
{
addr += dev->iobase;
*(volatile u16 *)(addr + 2) = swab16((u16)val);
*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

15
configs/rsk7269_defconfig
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@ -1,15 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0xDFC0000
CONFIG_TARGET_RSK7269=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC7,115200"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y

51
include/configs/rsk7269.h
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@ -1,51 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas RSK2+SH7269 board
*
* Copyright (C) 2012 Renesas Electronics Europe Ltd.
* Copyright (C) 2012 Phil Edworthy
*/
#ifndef __RSK7269_H
#define __RSK7269_H
#define CONFIG_CPU_SH7269 1
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
/* Serial */
#define CONFIG_CONS_SCIF7
/* Memory */
/* u-boot relocated to top 256KB of ram */
#define CONFIG_SYS_SDRAM_BASE 0x0C000000
#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
/* NOR Flash */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_ENV_OFFSET (128 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 66125000
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
#endif /* __RSK7269_H */