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drivers/ddr/fsl: Fix timing_cfg_2 register 

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-05-18 21:11:19 -07:00
parent c4f97b1f53
commit 5605dc6135
1 changed files with 1 additions and 1 deletions
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2
drivers/ddr/fsl/ctrl_regs.c
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@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
| ((add_lat_mclk & 0xf) << 28) | ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23) | ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19) | ((wr_lat & 0xf) << 19)
| ((wr_lat & 0x10) << 14) | ((wr_lat & 0x10) << 18)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6) | ((cke_pls & 0x7) << 6)