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pinctrl-snapdragon: Get rid of custom drive-strength values 

Use standard pinconf drive-strength values from Linux DT bindings rather
than ones based on custom u-boot header. These changes are in direction
to make u-boot DTs for Qcom SoCs to be compatible with standard Linux
DT bindings.

Also, add support for pinconf bias-pull-up.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg 2023-02-01 19:28:52 +05:30 committed by Tom Rini
parent c9062b3988
commit 56443285f2
6 changed files with 9 additions and 29 deletions
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3
arch/arm/dts/dragonboard410c.dts
View File

@ -9,7 +9,6 @@
#include "skeleton64.dtsi" #include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ { / {
model = "Qualcomm Technologies, Inc. Dragonboard 410c"; model = "Qualcomm Technologies, Inc. Dragonboard 410c";
@ -71,7 +70,7 @@
blsp1_uart: uart { blsp1_uart: uart {
function = "blsp1_uart"; function = "blsp1_uart";
pins = "GPIO_4", "GPIO_5"; pins = "GPIO_4", "GPIO_5";
drive-strength = <DRIVE_STRENGTH_8MA>; drive-strength = <8>;
bias-disable; bias-disable;
}; };
}; };

3
arch/arm/dts/dragonboard820c.dts
View File

@ -8,7 +8,6 @@
/dts-v1/; /dts-v1/;
#include "skeleton64.dtsi" #include "skeleton64.dtsi"
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ { / {
model = "Qualcomm Technologies, Inc. DB820c"; model = "Qualcomm Technologies, Inc. DB820c";
@ -71,7 +70,7 @@
blsp8_uart: uart { blsp8_uart: uart {
function = "blsp_uart8"; function = "blsp_uart8";
pins = "GPIO_4", "GPIO_5"; pins = "GPIO_4", "GPIO_5";
drive-strength = <DRIVE_STRENGTH_8MA>; drive-strength = <8>;
bias-disable; bias-disable;
}; };
}; };

1
arch/arm/dts/qcom-ipq4019.dtsi
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@ -9,7 +9,6 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h> #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h> #include <dt-bindings/reset/qcom,ipq4019-reset.h>

1
arch/arm/dts/qcs404-evb.dts
View File

@ -9,7 +9,6 @@
#include "skeleton64.dtsi" #include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h> #include <dt-bindings/clock/qcom,gcc-qcs404.h>
/ { / {

8
arch/arm/mach-snapdragon/pinctrl-snapdragon.c
View File

@ -28,8 +28,9 @@ struct msm_pinctrl_priv {
#define TLMM_GPIO_DISABLE BIT(9) #define TLMM_GPIO_DISABLE BIT(9)
static const struct pinconf_param msm_conf_params[] = { static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
}; };
static int msm_get_functions_count(struct udevice *dev) static int msm_get_functions_count(struct udevice *dev)
@ -89,6 +90,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
switch (param) { switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_DRIVE_STRENGTH:
argument = (argument / 2) - 1;
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_DRV_STRENGTH_MASK, argument << 6); TLMM_DRV_STRENGTH_MASK, argument << 6);
break; break;
@ -96,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_GPIO_PULL_MASK); TLMM_GPIO_PULL_MASK);
break; break;
case PIN_CONFIG_BIAS_PULL_UP:
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
default: default:
return 0; return 0;
} }

22
include/dt-bindings/pinctrl/pinctrl-snapdragon.h
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This header provides constants for Qualcomm Snapdragon pinctrl bindings.
*
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
*/
#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
/* GPIO Drive Strength */
#define DRIVE_STRENGTH_2MA 0
#define DRIVE_STRENGTH_4MA 1
#define DRIVE_STRENGTH_6MA 2
#define DRIVE_STRENGTH_8MA 3
#define DRIVE_STRENGTH_10MA 4
#define DRIVE_STRENGTH_12MA 5
#define DRIVE_STRENGTH_14MA 6
#define DRIVE_STRENGTH_16MA 7
#endif