From 56d95c60f1ec30b10e80672bbf5ba2ae89491900 Mon Sep 17 00:00:00 2001 From: Marcel Reichmuth Date: Mon, 21 Nov 2011 07:24:46 +0000 Subject: [PATCH] ADD: Basic ethernet support for HW08 SVN commit 8358@trunk --- board/netmodule/nbhw08/nbhw08.c | 52 ++++++++++++++++++--------------- drivers/net/tsec.c | 12 ++++++++ include/configs/NBHW08.h | 21 ++++++------- include/configs/NBHW09.h | 15 +++++----- net/eth.c | 6 ++++ 5 files changed, 65 insertions(+), 41 deletions(-) diff --git a/board/netmodule/nbhw08/nbhw08.c b/board/netmodule/nbhw08/nbhw08.c index f19a2c9c4d..25b046bbda 100644 --- a/board/netmodule/nbhw08/nbhw08.c +++ b/board/netmodule/nbhw08/nbhw08.c @@ -271,9 +271,6 @@ int board_early_init_f(void) udelay(12000); /* 12 ms */ gpio_regs_ptr->dat.reg |= MPC_GPIO_MASK(0); // remove reset - /* Configure the clock for USB controller */ - clrsetbits_be32(&clk->sccr, SCCR_USBDRCM, SCCR_USBDRCM_1); - /* Set USB DRIVE VBUS (GPIO8) High */ gpio_regs_ptr->dir.reg |= MPC_GPIO_MASK(8); gpio_regs_ptr->dat.reg |= MPC_GPIO_MASK(8); @@ -297,6 +294,18 @@ int board_early_init_f(void) TL_CPLD_REG(0x21) = 0x00; /* Apply power to all PCIe slots & GPS antenna */ + TL_CPLD_REG(0x31) = 0x01; + udelay(10000); /* 10 ms */ + TL_CPLD_REG(0x31) = 0x03; + udelay(10000); /* 10 ms */ + TL_CPLD_REG(0x31) = 0x07; + udelay(10000); /* 10 ms */ + TL_CPLD_REG(0x31) = 0x0f; + udelay(10000); /* 10 ms */ + TL_CPLD_REG(0x31) = 0x1f; + udelay(10000); /* 10 ms */ + TL_CPLD_REG(0x31) = 0x3f; + udelay(10000); /* 10 ms */ TL_CPLD_REG(0x31) = 0xbf; udelay(100000); /* 100 ms */ @@ -312,7 +321,7 @@ int board_early_init_f(void) TL_CPLD_REG(0xa0) = 0x20; TL_CPLD_REG(0xa2) = 0x20; - /* Get all PCIe slots auto of reset */ + /* Get all PCIe slots out of reset */ TL_CPLD_REG(0x30) = 0x00; udelay(12000); /* 12 ms */ TL_CPLD_REG(0x30) = 0x3f; @@ -425,7 +434,7 @@ void pci_init_board(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -// fdt_fixup_dr_usb(blob, bd); + fdt_fixup_dr_usb(blob, bd); } #endif /* CONFIG_OF_BOARD_SETUP */ @@ -440,28 +449,23 @@ void ft_board_setup(void *blob, bd_t *bd) */ static void init_phy(void) { - char *devname; - - /* Use current device (only one device is registered: eTSECO). - * The device has already been registered by the function eth_initialize(...). - */ - devname = miiphy_get_current_dev(); - + char *devname = CONFIG_TSEC1_NAME; + /* Disable bridging between external ethernet ports */ - miiphy_write(devname, 0x00, 0x06, 0x0020); - miiphy_write(devname, 0x01, 0x06, 0x0020); - miiphy_write(devname, 0x02, 0x06, 0x0020); - miiphy_write(devname, 0x03, 0x06, 0x0020); - miiphy_write(devname, 0x04, 0x06, 0x0020); - miiphy_write(devname, 0x05, 0x06, 0x001f); + miiphy_write(devname, 0x08, 0x06, 0x0020); + miiphy_write(devname, 0x09, 0x06, 0x0020); + miiphy_write(devname, 0x0a, 0x06, 0x0020); + miiphy_write(devname, 0x0b, 0x06, 0x0020); + miiphy_write(devname, 0x0c, 0x06, 0x0020); + miiphy_write(devname, 0x0d, 0x06, 0x001f); /* Enable all ethernet ports */ - miiphy_write(devname, 0x00, 0x04, 0x0003); - miiphy_write(devname, 0x01, 0x04, 0x0003); - miiphy_write(devname, 0x02, 0x04, 0x0003); - miiphy_write(devname, 0x03, 0x04, 0x0003); - miiphy_write(devname, 0x04, 0x04, 0x0003); - miiphy_write(devname, 0x05, 0x04, 0x0003); + miiphy_write(devname, 0x08, 0x04, 0x0003); + miiphy_write(devname, 0x09, 0x04, 0x0003); + miiphy_write(devname, 0x0a, 0x04, 0x0003); + miiphy_write(devname, 0x0b, 0x04, 0x0003); + miiphy_write(devname, 0x0c, 0x04, 0x0003); + miiphy_write(devname, 0x0d, 0x04, 0x0003); } int board_eth_init(bd_t *bis) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5a541557a9..dea95edba8 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1827,6 +1827,18 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) uint result; volatile tsec_t *phyregs = priv->phyregs; +#ifdef NBHW08 + /* @@NM@@MR@ Hardcode link settings for TSEC1 on NBHW08, + because it does not have a PHY */ + if (priv->regs==0xe0025000) + { + priv->link=1; + priv->speed=100; + priv->duplexity=1; + return; + } +#endif + phyregs->miimcfg = MIIMCFG_RESET; phyregs->miimcfg = MIIMCFG_INIT_VALUE; diff --git a/include/configs/NBHW08.h b/include/configs/NBHW08.h index 82eb704bf3..0d052bfee7 100755 --- a/include/configs/NBHW08.h +++ b/include/configs/NBHW08.h @@ -57,6 +57,7 @@ #define CONFIG_MPC831x 1 /* MPC831x CPU family */ #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_NMCP 1 /* NMCP board specific */ +#define NBHW08 1 /* NETBOX hardware platform is 08 */ /* Remove unused functions from UART driver in bootstrap to save precious space */ #ifdef CONFIG_NAND_SPL @@ -94,7 +95,7 @@ HRCWH_ROM_LOC_NAND_LP_8BIT |\ HRCWH_RL_EXT_NAND |\ HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_TSEC2M_IN_MII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) @@ -110,7 +111,7 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_TSEC2M_IN_MII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) @@ -120,7 +121,7 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0xffff0fc3 /* GPIO26/27 used, USB, GTX_CLK125/MDC/MDIO = 3.3V, no delay, TSEC output buffer = 2.5V */ +#define CONFIG_SYS_SICRH 0xffff0f02 /* GPIO26/27 used, USB, GTX_CLK125/MDC/MDIO = 3.3V, no delay, TSEC1 output buffer = 2.5V, TSEC2 output buffer = 3.3V */ #define CONFIG_SYS_SICRL 0xf00f0001 /* TSEC output buffer = 2.5V (not sure) */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ @@ -541,7 +542,7 @@ #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_SYS_SCCR_USBDRCM 3 +#define CONFIG_SYS_SCCR_USBDRCM 1 #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI @@ -576,18 +577,17 @@ #define TSEC1_PHYIDX 0 #define TSEC1_FLAGS TSEC_GIGABIT -#if 0 #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC2_PHY_ADDR 4 +#define TSEC2_PHY_ADDR 0 #define TSEC2_PHYIDX 0 #define TSEC2_FLAGS 0 /* TSEC_GIGABIT */ -#endif + #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with Ethernet PHYs */ /* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_ETHPRIME "eTSEC1" /* @@ -804,10 +804,11 @@ "imgaddr=2800000\0" \ "imgfile=kernel.bin\0" \ "fdtaddr=2700000\0" \ - "fdtfile=nbhw09.dtb\0" \ + "fdtfile=nbhw08.dtb\0" \ "imgrcv=recovery-image\0" \ "fdtrcv=recovery-dtb\0" \ - "usb_phy_type=ulpi\0" \ + "usb_phy_type=utmi\0" \ + "ethprime=eTSEC1\0" \ "recovery=setenv bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $mtdparts $othbootargs;" \ diff --git a/include/configs/NBHW09.h b/include/configs/NBHW09.h index 561c8a0c3f..050d216d63 100644 --- a/include/configs/NBHW09.h +++ b/include/configs/NBHW09.h @@ -54,8 +54,9 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC831x 1 /* MPC831x CPU family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ -#define CONFIG_NETBOX 1 /* NETBOX board specific */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_NETBOX 1 /* NETBOX board specific */ +#define NBHW09 1 /* NETBOX hardware platform is 09*/ /* Remove unused functions from UART driver in bootstrap to save precious space */ #ifdef CONFIG_NAND_SPL @@ -685,13 +686,13 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L @@ -712,19 +713,19 @@ #endif /* Stack in dcache : cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L diff --git a/net/eth.c b/net/eth.c index 9410c68ada..4a71d899c6 100644 --- a/net/eth.c +++ b/net/eth.c @@ -236,6 +236,12 @@ int eth_initialize(bd_t *bis) /* Get MAC address from board descriptor */ settings_get_mac(eth_number, env_enetaddr); + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + /* @@NM@MR@@ Use MAC of first interface multiple times, + if we have not enough MAC addresses. */ + settings_get_mac(0, env_enetaddr); + } + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) == 0) { /* No MAC address in board descriptor found, use default */ eth_parse_enetaddr(CONFIG_ETHADDR_DEFAULT, env_enetaddr);