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MLK-18346 imx: 8mm_evk: remove the duplicated performance settings 

There is already a PERF_TEST_2 macro controlling the performance
settings.
Also the removed settings in this patch is directly copied
from i.MX8MQ which is not that correct in some settings,
so remove them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0c8c6f616c8c819e986d4246f744e8ef7aed0919)
This commit is contained in:
Peng Fan 2018-05-29 14:43:52 +08:00 committed by Ye Li
parent 81e64d882c
commit 58b397a06a
1 changed files with 0 additions and 24 deletions
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24
board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c
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@ -239,30 +239,6 @@ static struct ddr_ctl_param ctl_init_cfg[] =
{ .reg =DDRC_MSTR2(0), .val = 0x0}, { .reg =DDRC_MSTR2(0), .val = 0x0},
#endif #endif
#endif #endif
{ .reg = DDRC_ODTCFG(0), 0x0b060908},
{ .reg = DDRC_ODTMAP(0), 0x00000000},
{ .reg = DDRC_SCHED(0), 0x29511505},
{ .reg = DDRC_SCHED1(0), 0x0000002c},
{ .reg = DDRC_PERFHPR1(0), 0x5900575b},
{ .reg = DDRC_PERFLPR1(0), 0x00000009},
{ .reg = DDRC_PERFWR1(0), 0x02005574},
{ .reg = DDRC_DBG0(0), 0x00000016},
{ .reg = DDRC_DBG1(0), 0x00000000},
{ .reg = DDRC_DBGCMD(0), 0x00000000},
{ .reg = DDRC_SWCTL(0), 0x00000001},
{ .reg = DDRC_POISONCFG(0), 0x00000011},
{ .reg = DDRC_PCCFG(0), 0x00000111},
{ .reg = DDRC_PCFGR_0(0), 0x000010f3},
{ .reg = DDRC_PCFGW_0(0), 0x000072ff},
{ .reg = DDRC_PCTRL_0(0), 0x00000001},
{ .reg = DDRC_PCFGQOS0_0(0), 0x01110d00},
{ .reg = DDRC_PCFGQOS1_0(0), 0x00620790},
{ .reg = DDRC_PCFGWQOS0_0(0), 0x00100001},
{ .reg = DDRC_PCFGWQOS1_0(0), 0x0000041f},
{ .reg = DDRC_FREQ1_DERATEEN(0), 0x00000202},
{ .reg = DDRC_FREQ1_DERATEINT(0), 0xec78f4b5},
{ .reg = DDRC_FREQ1_RFSHCTL0(0), 0x00618040},
{ .reg = DDRC_FREQ1_RFSHTMG(0), 0x00610090},
}; };
void lpddr4_3000mts_cfg_umctl2(void) void lpddr4_3000mts_cfg_umctl2(void)