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Some fixes to dspic, fpga, and gdc post tests for lwmon5. 

Disable external watch-dog for now.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
This commit is contained in:
Yuri Tikhonov 2008-02-04 17:09:55 +01:00 committed by Wolfgang Denk
parent e262efe357
commit 603f194e5a
3 changed files with 6 additions and 2 deletions
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2
post/board/lwmon5/dspic.c
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@ -94,9 +94,9 @@ int dspic_post_test(int flags)
} }
data = dspic_read(DSPIC_SYS_ERROR_REG); data = dspic_read(DSPIC_SYS_ERROR_REG);
if (data != 0) ret = 1;
if (data == -1) { if (data == -1) {
post_log("dsPIC : failed read system error\n"); post_log("dsPIC : failed read system error\n");
ret = 1;
} else { } else {
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
} }

4
post/board/lwmon5/fpga.c
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@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define FPGA_VERSION_REG 0xC4000040 #define FPGA_VERSION_REG 0xC4000040
#define FPGA_RAM_START 0xC4200000 #define FPGA_RAM_START 0xC4200000
#define FPGA_RAM_END 0xC4203FFF #define FPGA_RAM_END 0xC4203FFF
#define FPGA_STAT 0xC400000C
#define FPGA_PWM_CTRL_REG 0xC4000020 #define FPGA_PWM_CTRL_REG 0xC4000020
#define FPGA_PWM_TV_REG 0xC4000024 #define FPGA_PWM_TV_REG 0xC4000024
@ -93,6 +94,9 @@ int fpga_post_test(int flags)
post_log("FPGA : version %u.%u\n", post_log("FPGA : version %u.%u\n",
(version >> 8) & 0xFF, version & 0xFF); (version >> 8) & 0xFF, version & 0xFF);
/* Enable write to FPGA RAM */
out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000); read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
post_log("FPGA RAM size: %d bytes\n", read_value); post_log("FPGA RAM size: %d bytes\n", read_value);

2
post/board/lwmon5/gdc.c
View File

@ -35,7 +35,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define GDC_SCRATCH_REG 0xC1FF8044 #define GDC_SCRATCH_REG 0xC1FF8008
#define GDC_VERSION_REG 0xC1FF8084 #define GDC_VERSION_REG 0xC1FF8084
#define GDC_RAM_START 0xC0000000 #define GDC_RAM_START 0xC0000000
#define GDC_RAM_END 0xC2000000 #define GDC_RAM_END 0xC2000000