arm: dts: k3-am642-evm: Add NAND support
Add NAND support for A53 SPL, u-boot and R5 SPL. For A53 SPL & u-boot we use NAND overlay to add NAND support. For R5 SPL, we include the NAND support in the board DTS file (k3-am642-r5-evm.dts) as there is no way to use overlay in BootROM at the moment. Signed-off-by: Roger Quadros <rogerq@kernel.org>
This commit is contained in:
Roger Quadros
Praneeth Bajjuri
parent
1c738366e8
commit
62ec935c3f
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@ -987,7 +987,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
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k3-am642-r5-evm.dtb \
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k3-am642-sk.dtb \
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k3-am642-r5-sk.dtb
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k3-am642-r5-sk.dtb \
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k3-am642-evm-nand.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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@ -0,0 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0
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/**
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* DT overlay for HSE NAND expansion card on AM642 EVM
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include "k3-am642-evm-nand.dtsi"
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@ -0,0 +1,129 @@
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// SPDX-License-Identifier: GPL-2.0
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/**
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* DT overlay for HSE NAND expansion card on AM642 EVM
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&main_pmx0 {
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gpmc0_pins_default: gpmc0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
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AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */
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AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */
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AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */
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AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */
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AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */
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AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */
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AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */
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AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */
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AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */
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AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */
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AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */
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AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */
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AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */
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AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */
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AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */
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AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */
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AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */
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AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */
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AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */
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AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */
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AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */
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AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */
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AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */
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AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */
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AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */
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AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */
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AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */
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AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */
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AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */
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>;
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};
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};
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&main_gpio0 {
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gpio0-36 {
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gpio-hog;
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gpios = <36 0>;
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input;
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line-name = "GPMC0_MUX_DIR";
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};
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};
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&gpmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpmc0_pins_default>;
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ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
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#address-cells = <2>;
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#size-cells = <1>;
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nand0_0: nand@0,0 {
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compatible = "ti,am64-nand";
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reg = <0 0 64>; /* device IO registers */
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interrupt-parent = <&gpmc0>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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ti,nand-xfer-type = "prefetch-polled";
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ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
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ti,elm-id = <&elm0>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <40>;
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gpmc,cs-wr-off-ns = <40>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <25>;
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gpmc,adv-wr-off-ns = <25>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <20>;
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gpmc,oe-on-ns = <3>;
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gpmc,oe-off-ns = <30>;
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gpmc,access-ns = <30>;
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.tiboot3";
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reg = <0x00000000 0x00200000>; /* 2M */
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};
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partition@200000 {
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label = "NAND.tispl";
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reg = <0x00200000 0x00200000>; /* 2M */
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};
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partition@400000 {
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label = "NAND.tiboot3.backup"; /* 2M */
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reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
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};
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partition@600000 {
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label = "NAND.u-boot";
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reg = <0x00600000 0x00400000>; /* 4M */
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};
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partition@a00000 {
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label = "NAND.u-boot-env";
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reg = <0x00a00000 0x00040000>; /* 256K */
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};
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partition@a40000 {
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label = "NAND.u-boot-env.backup";
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reg = <0x00a40000 0x00040000>; /* 256K */
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};
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partition@a80000 {
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label = "NAND.file-system";
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reg = <0x00a80000 0x3f580000>;
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};
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};
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};
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};
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@ -283,4 +283,22 @@
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/delete-property/ power-domains;
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};
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#include "k3-am642-evm-nand.dtsi"
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&gpmc0_pins_default {
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u-boot,dm-spl;
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};
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&gpmc0 {
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u-boot,dm-spl;
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};
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&main_gpio0 {
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u-boot,dm-spl;
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};
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&nand0_0 {
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u-boot,dm-spl;
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};
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#include "k3-am642-evm-u-boot.dtsi"
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