arm: Remove pcm051 board
OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Acked-by: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
parent
a9c84ffa99
commit
64efd11d3b
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@ -1905,7 +1905,6 @@ source "board/hisilicon/hikey/Kconfig"
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source "board/hisilicon/hikey960/Kconfig"
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source "board/hisilicon/hikey960/Kconfig"
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source "board/hisilicon/poplar/Kconfig"
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source "board/hisilicon/poplar/Kconfig"
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source "board/isee/igep003x/Kconfig"
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source "board/isee/igep003x/Kconfig"
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source "board/phytec/pcm051/Kconfig"
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source "board/silica/pengwyn/Kconfig"
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source "board/silica/pengwyn/Kconfig"
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source "board/spear/spear300/Kconfig"
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source "board/spear/spear300/Kconfig"
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source "board/spear/spear310/Kconfig"
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source "board/spear/spear310/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_PCM051
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config SYS_BOARD
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default "pcm051"
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config SYS_VENDOR
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default "phytec"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "pcm051"
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endif
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@ -1,7 +0,0 @@
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PCM051 BOARD
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M: Lars Poeschel <poeschel@lemonage.de>
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S: Maintained
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F: board/phytec/pcm051/
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F: include/configs/pcm051.h
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F: configs/pcm051_rev1_defconfig
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F: configs/pcm051_rev3_defconfig
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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ifdef CONFIG_SPL_BUILD
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obj-y += mux.o
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endif
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obj-y += board.o
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@ -1,258 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for Phytec phyCORE-AM335x (pcm051) based boards
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*
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* Copyright (C) 2013 Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <net.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* MII mode defines */
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#define RMII_RGMII2_MODE_ENABLE 0x49
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#ifdef CONFIG_SPL_BUILD
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/* DDR RAM defines */
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#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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}
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#ifdef CONFIG_REV1
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
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.cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
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.cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
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.dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
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.dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
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};
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J256M8HX15E_RD_DQS,
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.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
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.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
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.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41J256M8HX15E_RATIO,
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.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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.cmd1csratio = MT41J256M8HX15E_RATIO,
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.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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.cmd2csratio = MT41J256M8HX15E_RATIO,
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.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
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.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
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.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
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.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
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.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
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.zq_config = MT41J256M8HX15E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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void sdram_init(void)
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{
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config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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#else
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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void sdram_init(void)
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{
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config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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#endif
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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enable_board_pin_mux();
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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#ifdef CONFIG_DRIVER_TI_CPSW
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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printf("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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else
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goto try_usbether;
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}
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writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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try_usbether:
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#endif
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#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
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rv = usb_eth_initialize(bis);
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if (rv < 0)
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printf("Error %d registering USB_ETHER\n", rv);
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else
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n += rv;
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#endif
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return n;
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}
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#endif
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@ -1,24 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* board.h
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*
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* Phytec phyCORE-AM335x (pcm051) boards information header
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*
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* Copyright (C) 2013, Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* We have three pin mux functions that must exist. We must be able to enable
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* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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void enable_board_pin_mux(void);
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void enable_cbmux_pin_mux(void);
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#endif
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/*
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* mux.c
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*
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* Copyright (C) 2013 Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include "board.h"
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|
||||||
static struct module_pin_mux uart0_pin_mux[] = {
|
|
||||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
|
||||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_MMC
|
|
||||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
|
||||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
|
||||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
|
||||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
|
||||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
|
||||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
|
||||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
|
||||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_I2C
|
|
||||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
|
||||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
|
||||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
|
||||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
|
||||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI
|
|
||||||
static struct module_pin_mux spi0_pin_mux[] = {
|
|
||||||
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
|
|
||||||
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
|
|
||||||
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
|
|
||||||
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
|
|
||||||
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
|
|
||||||
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static struct module_pin_mux rmii1_pin_mux[] = {
|
|
||||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
|
|
||||||
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
|
|
||||||
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
|
|
||||||
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
|
|
||||||
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
|
|
||||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
|
|
||||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
|
|
||||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
|
||||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
|
||||||
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct module_pin_mux cbmux_pin_mux[] = {
|
|
||||||
{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
|
|
||||||
{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_MTD_RAW_NAND
|
|
||||||
static struct module_pin_mux nand_pin_mux[] = {
|
|
||||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
|
||||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
|
||||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
|
||||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
|
||||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
|
||||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
|
||||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
|
||||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
|
||||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
|
||||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
|
||||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
|
||||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
|
||||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
|
||||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
|
||||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
|
||||||
{-1},
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void enable_uart0_pin_mux(void)
|
|
||||||
{
|
|
||||||
configure_module_pin_mux(uart0_pin_mux);
|
|
||||||
}
|
|
||||||
|
|
||||||
void enable_i2c0_pin_mux(void)
|
|
||||||
{
|
|
||||||
configure_module_pin_mux(i2c0_pin_mux);
|
|
||||||
}
|
|
||||||
|
|
||||||
void enable_board_pin_mux()
|
|
||||||
{
|
|
||||||
configure_module_pin_mux(rmii1_pin_mux);
|
|
||||||
configure_module_pin_mux(mmc0_pin_mux);
|
|
||||||
configure_module_pin_mux(cbmux_pin_mux);
|
|
||||||
#ifdef CONFIG_MTD_RAW_NAND
|
|
||||||
configure_module_pin_mux(nand_pin_mux);
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_SPI
|
|
||||||
configure_module_pin_mux(spi0_pin_mux);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
@ -1,60 +0,0 @@
|
||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_ARCH_CPU_INIT=y
|
|
||||||
CONFIG_ARCH_OMAP2PLUS=y
|
|
||||||
CONFIG_SPL_GPIO_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
||||||
CONFIG_AM33XX=y
|
|
||||||
CONFIG_TARGET_PCM051=y
|
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
|
||||||
CONFIG_SPL=y
|
|
||||||
CONFIG_SPL_FS_FAT=y
|
|
||||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="REV1"
|
|
||||||
# CONFIG_USE_BOOTCOMMAND is not set
|
|
||||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
||||||
CONFIG_VERSION_VARIABLE=y
|
|
||||||
CONFIG_ARCH_MISC_INIT=y
|
|
||||||
CONFIG_SPL_ENV_SUPPORT=y
|
|
||||||
CONFIG_SPL_ETH_SUPPORT=y
|
|
||||||
CONFIG_SPL_FS_EXT4=y
|
|
||||||
CONFIG_SPL_I2C_SUPPORT=y
|
|
||||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
|
||||||
CONFIG_SPL_NET_SUPPORT=y
|
|
||||||
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
|
|
||||||
CONFIG_SPL_OS_BOOT=y
|
|
||||||
CONFIG_SPL_POWER_SUPPORT=y
|
|
||||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
|
||||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
|
||||||
CONFIG_CMD_SPL=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_GPIO=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_SF=y
|
|
||||||
CONFIG_CMD_SPI=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
||||||
CONFIG_MMC_OMAP_HS=y
|
|
||||||
CONFIG_SPI_FLASH=y
|
|
||||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
|
||||||
CONFIG_SPI_FLASH_WINBOND=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_DRIVER_TI_CPSW=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_OMAP3_SPI=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_MUSB_HOST=y
|
|
||||||
CONFIG_USB_MUSB_GADGET=y
|
|
||||||
CONFIG_USB_MUSB_DSPS=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETHER=y
|
|
||||||
CONFIG_FAT_WRITE=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,60 +0,0 @@
|
||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_ARCH_CPU_INIT=y
|
|
||||||
CONFIG_ARCH_OMAP2PLUS=y
|
|
||||||
CONFIG_SPL_GPIO_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
||||||
CONFIG_AM33XX=y
|
|
||||||
CONFIG_TARGET_PCM051=y
|
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
|
||||||
CONFIG_SPL=y
|
|
||||||
CONFIG_SPL_FS_FAT=y
|
|
||||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="REV3"
|
|
||||||
# CONFIG_USE_BOOTCOMMAND is not set
|
|
||||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
||||||
CONFIG_VERSION_VARIABLE=y
|
|
||||||
CONFIG_ARCH_MISC_INIT=y
|
|
||||||
CONFIG_SPL_ENV_SUPPORT=y
|
|
||||||
CONFIG_SPL_ETH_SUPPORT=y
|
|
||||||
CONFIG_SPL_FS_EXT4=y
|
|
||||||
CONFIG_SPL_I2C_SUPPORT=y
|
|
||||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
|
||||||
CONFIG_SPL_NET_SUPPORT=y
|
|
||||||
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
|
|
||||||
CONFIG_SPL_OS_BOOT=y
|
|
||||||
CONFIG_SPL_POWER_SUPPORT=y
|
|
||||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
|
||||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
|
||||||
CONFIG_CMD_SPL=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_GPIO=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_SF=y
|
|
||||||
CONFIG_CMD_SPI=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
||||||
CONFIG_MMC_OMAP_HS=y
|
|
||||||
CONFIG_SPI_FLASH=y
|
|
||||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
|
||||||
CONFIG_SPI_FLASH_WINBOND=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_DRIVER_TI_CPSW=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_OMAP3_SPI=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_MUSB_HOST=y
|
|
||||||
CONFIG_USB_MUSB_GADGET=y
|
|
||||||
CONFIG_USB_MUSB_DSPS=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETHER=y
|
|
||||||
CONFIG_FAT_WRITE=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,128 +0,0 @@
|
||||||
/*
|
|
||||||
* pcm051.h
|
|
||||||
*
|
|
||||||
* Phytec phyCORE-AM335x (pcm051) boards information header
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Lemonage Software GmbH
|
|
||||||
* Author Lars Poeschel <poeschel@lemonage.de>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation version 2.
|
|
||||||
*
|
|
||||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
||||||
* kind, whether express or implied; without even the implied warranty
|
|
||||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_PCM051_H
|
|
||||||
#define __CONFIG_PCM051_H
|
|
||||||
|
|
||||||
#include <configs/ti_am335x_common.h>
|
|
||||||
|
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
|
|
||||||
|
|
||||||
/* set to negative value for no autoboot */
|
|
||||||
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
|
|
||||||
"bootcmd_" #devtypel #instance "=" \
|
|
||||||
"setenv mmcdev " #instance"; "\
|
|
||||||
"setenv bootpart " #instance":2 ; "\
|
|
||||||
"run mmcboot\0"
|
|
||||||
|
|
||||||
#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
|
|
||||||
#devtypel #instance " "
|
|
||||||
|
|
||||||
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
|
|
||||||
"bootcmd_" #devtypel "=" \
|
|
||||||
"run nandboot\0"
|
|
||||||
|
|
||||||
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
|
|
||||||
#devtypel #instance " "
|
|
||||||
|
|
||||||
#define BOOT_TARGET_DEVICES(func) \
|
|
||||||
func(MMC, mmc, 0) \
|
|
||||||
func(LEGACY_MMC, legacy_mmc, 0) \
|
|
||||||
func(MMC, mmc, 1) \
|
|
||||||
func(LEGACY_MMC, legacy_mmc, 1) \
|
|
||||||
func(NAND, nand, 0)
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND \
|
|
||||||
"run distro_bootcmd"
|
|
||||||
|
|
||||||
#include <config_distro_bootcmd.h>
|
|
||||||
|
|
||||||
#include <environment/ti/dfu.h>
|
|
||||||
#include <environment/ti/mmc.h>
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
DEFAULT_LINUX_BOOT_ENV \
|
|
||||||
DEFAULT_MMC_TI_ARGS \
|
|
||||||
"bootfile=uImage\0" \
|
|
||||||
"fdtfile=am335x-wega-rdk.dtb\0" \
|
|
||||||
"console=ttyO0,115200n8\0" \
|
|
||||||
"optargs=\0" \
|
|
||||||
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
|
||||||
"ramrootfstype=ext2\0" \
|
|
||||||
"bootenv=uEnv.txt\0" \
|
|
||||||
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
|
||||||
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
|
|
||||||
"source ${loadaddr}\0" \
|
|
||||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
|
||||||
"importbootenv=echo Importing environment from mmc ...; " \
|
|
||||||
"env import -t $loadaddr $filesize\0" \
|
|
||||||
"ramargs=setenv bootargs console=${console} " \
|
|
||||||
"${optargs} " \
|
|
||||||
"root=${ramroot} " \
|
|
||||||
"rootfstype=${ramrootfstype}\0" \
|
|
||||||
"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
|
||||||
"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
|
|
||||||
"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
|
|
||||||
"mmcboot=echo Booting from mmc ...; " \
|
|
||||||
"run args_mmc; " \
|
|
||||||
"bootm ${loadaddr}\0" \
|
|
||||||
"ramboot=echo Booting from ramdisk ...; " \
|
|
||||||
"run ramargs; " \
|
|
||||||
"bootm ${loadaddr}\0" \
|
|
||||||
BOOTENV
|
|
||||||
|
|
||||||
/* Clock Defines */
|
|
||||||
#define V_OSCK 25000000 /* Clock output from T2 */
|
|
||||||
#define V_SCLK (V_OSCK)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* memtest works on 8 MB in DRAM after skipping 32MB from
|
|
||||||
* start addr of ram disk
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* NS16550 Configuration */
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
|
||||||
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
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||||||
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
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||||||
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
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|
||||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
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|
||||||
|
|
||||||
/* I2C Configuration */
|
|
||||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
|
|
||||||
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
|
|
||||||
|
|
||||||
/* CPU */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_BOOT
|
|
||||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_AM335X_USB0
|
|
||||||
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
|
||||||
#define CONFIG_AM335X_USB1
|
|
||||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
|
||||||
|
|
||||||
#endif /* ! __CONFIG_PCM051_H */
|
|
||||||
Loading…
Reference in New Issue