Factor out SC520 sub-features
Moved sub-features of the SC520 code which is currently selectively compiled using #ifdef out of sc520.c into individual files selectively compiled via the makefile Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
This commit is contained in:
Graeme Russ
Wolfgang Denk
parent
abf0cd3dff
commit
6d7f610b09
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@ -32,6 +32,10 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)lib$(SOC).a
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COBJS-$(CONFIG_SYS_SC520) += sc520.o
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COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
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COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
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COBJS-$(CONFIG_PCI) += sc520_pci.o
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SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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@ -24,15 +24,8 @@
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/* stuff specific for the sc520,
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* but idependent of implementation */
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#include <config.h>
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#include <common.h>
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#include <config.h>
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#include <pci.h>
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#ifdef CONFIG_SYS_SC520_SSI
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#include <asm/ic/ssi.h>
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#endif
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/ic/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -50,13 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
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*
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* void init_sc520(void)
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* unsigned long init_sc520_dram(void)
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* void pci_sc520_init(struct pci_controller *hose)
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*
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* void reset_timer(void)
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* ulong get_timer(ulong base)
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* void set_timer(ulong t)
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* void udelay(unsigned long usec)
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*
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*/
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static u32 mmcr_base= 0xfffef000;
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@ -241,269 +227,6 @@ unsigned long init_sc520_dram(void)
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return dram_present;
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}
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#ifdef CONFIG_PCI
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static struct {
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u8 priority;
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u16 level_reg;
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u8 level_bit;
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} sc520_irq[] = {
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{ SC520_IRQ0, SC520_MPICMODE, 0x01 },
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{ SC520_IRQ1, SC520_MPICMODE, 0x02 },
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{ SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ3, SC520_MPICMODE, 0x08 },
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{ SC520_IRQ4, SC520_MPICMODE, 0x10 },
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{ SC520_IRQ5, SC520_MPICMODE, 0x20 },
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{ SC520_IRQ6, SC520_MPICMODE, 0x40 },
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{ SC520_IRQ7, SC520_MPICMODE, 0x80 },
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{ SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
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{ SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
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{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
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{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
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{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
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{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
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{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
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};
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/* The interrupt used for PCI INTA-INTD */
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int sc520_pci_ints[15] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1
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};
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/* utility function to configure a pci interrupt */
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int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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# if 1
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printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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#endif
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if (irq < 0 || irq > 15) {
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return -1; /* illegal irq */
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}
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if (pci_pin < 0 || pci_pin > 15) {
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return -1; /* illegal pci int pin */
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}
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/* first disable any non-pci interrupt source that use
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* this level */
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for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
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if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
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continue;
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}
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if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
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write_mmcr_byte(i, SC520_IRQ_DISABLED);
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}
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}
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/* Set the trigger to level */
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write_mmcr_byte(sc520_irq[irq].level_reg,
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read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
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if (pci_pin < 4) {
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/* PCI INTA-INTD */
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/* route the interrupt */
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write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
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} else {
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/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
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write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
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/* also set the polarity in this case */
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write_mmcr_word(SC520_INTPINPOL,
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read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
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}
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/* register the pin */
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sc520_pci_ints[pci_pin] = irq;
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return 0; /* OK */
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}
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void pci_sc520_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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SC520_PCI_MEMORY_BUS,
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SC520_PCI_MEMORY_PHYS,
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SC520_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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SC520_PCI_MEM_BUS,
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SC520_PCI_MEM_PHYS,
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SC520_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* ISA/PCI memory space */
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pci_set_region(hose->regions + 2,
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SC520_ISA_MEM_BUS,
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SC520_ISA_MEM_PHYS,
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SC520_ISA_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 3,
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SC520_PCI_IO_BUS,
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SC520_PCI_IO_PHYS,
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SC520_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* ISA/PCI I/O space */
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pci_set_region(hose->regions + 4,
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SC520_ISA_IO_BUS,
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SC520_ISA_IO_PHYS,
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SC520_ISA_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 5;
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pci_setup_type1(hose,
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SC520_REG_ADDR,
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SC520_REG_DATA);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* enable target memory acceses on host brige */
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pci_write_config_word(0, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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#endif
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#ifdef CONFIG_SYS_SC520_TIMER
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void reset_timer(void)
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{
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write_mmcr_word(SC520_GPTMR0CNT, 0);
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write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
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}
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ulong get_timer(ulong base)
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{
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/* fixme: 30 or 33 */
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return read_mmcr_word(SC520_GPTMR0CNT) / 33;
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}
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void set_timer(ulong t)
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{
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/* FixMe: use two cascade coupled timers */
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write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
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write_mmcr_word(SC520_GPTMR0CNT, t*33);
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write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
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}
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void udelay(unsigned long usec)
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{
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int m=0;
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long u;
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read_mmcr_word(SC520_SWTMRMILLI);
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read_mmcr_word(SC520_SWTMRMICRO);
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#if 0
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/* do not enable this line, udelay is used in the serial driver -> recursion */
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printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
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#endif
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while (1) {
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m += read_mmcr_word(SC520_SWTMRMILLI);
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u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
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if (usec <= u) {
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break;
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}
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}
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}
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#endif
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int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
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{
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u8 temp=0;
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if (freq >= 8192) {
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temp |= CTL_CLK_SEL_4;
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} else if (freq >= 4096) {
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temp |= CTL_CLK_SEL_8;
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} else if (freq >= 2048) {
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temp |= CTL_CLK_SEL_16;
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} else if (freq >= 1024) {
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temp |= CTL_CLK_SEL_32;
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} else if (freq >= 512) {
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temp |= CTL_CLK_SEL_64;
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} else if (freq >= 256) {
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temp |= CTL_CLK_SEL_128;
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} else if (freq >= 128) {
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temp |= CTL_CLK_SEL_256;
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} else {
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temp |= CTL_CLK_SEL_512;
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}
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if (!lsb_first) {
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temp |= MSBF_ENB;
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}
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if (inv_clock) {
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temp |= CLK_INV_ENB;
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}
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if (inv_phase) {
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temp |= PHS_INV_ENB;
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}
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write_mmcr_byte(SC520_SSICTL, temp);
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return 0;
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}
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u8 ssi_txrx_byte(u8 data)
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{
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write_mmcr_byte(SC520_SSIXMIT, data);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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return read_mmcr_byte(SC520_SSIRCV);
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}
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void ssi_tx_byte(u8 data)
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{
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write_mmcr_byte(SC520_SSIXMIT, data);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
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}
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u8 ssi_rx_byte(void)
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{
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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return read_mmcr_byte(SC520_SSIRCV);
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}
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#ifdef CONFIG_SYS_SC520_RESET
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void reset_cpu(ulong addr)
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{
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@ -0,0 +1,171 @@
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/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* stuff specific for the sc520, but independent of implementation */
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/ic/sc520.h>
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static struct {
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u8 priority;
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u16 level_reg;
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u8 level_bit;
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} sc520_irq[] = {
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{ SC520_IRQ0, SC520_MPICMODE, 0x01 },
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{ SC520_IRQ1, SC520_MPICMODE, 0x02 },
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{ SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ3, SC520_MPICMODE, 0x08 },
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{ SC520_IRQ4, SC520_MPICMODE, 0x10 },
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{ SC520_IRQ5, SC520_MPICMODE, 0x20 },
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{ SC520_IRQ6, SC520_MPICMODE, 0x40 },
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{ SC520_IRQ7, SC520_MPICMODE, 0x80 },
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{ SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
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{ SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
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{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
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{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
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{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
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{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
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{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
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};
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/* The interrupt used for PCI INTA-INTD */
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int sc520_pci_ints[15] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1
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};
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/* utility function to configure a pci interrupt */
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int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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# if 1
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printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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#endif
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if (irq < 0 || irq > 15) {
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return -1; /* illegal irq */
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}
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if (pci_pin < 0 || pci_pin > 15) {
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return -1; /* illegal pci int pin */
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}
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/* first disable any non-pci interrupt source that use
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* this level */
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for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
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if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
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continue;
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}
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if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
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write_mmcr_byte(i, SC520_IRQ_DISABLED);
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}
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}
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/* Set the trigger to level */
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write_mmcr_byte(sc520_irq[irq].level_reg,
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read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
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if (pci_pin < 4) {
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/* PCI INTA-INTD */
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/* route the interrupt */
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write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
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} else {
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/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
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write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
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/* also set the polarity in this case */
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write_mmcr_word(SC520_INTPINPOL,
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read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
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}
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/* register the pin */
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sc520_pci_ints[pci_pin] = irq;
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return 0; /* OK */
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}
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void pci_sc520_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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SC520_PCI_MEMORY_BUS,
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SC520_PCI_MEMORY_PHYS,
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SC520_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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SC520_PCI_MEM_BUS,
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SC520_PCI_MEM_PHYS,
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SC520_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* ISA/PCI memory space */
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pci_set_region(hose->regions + 2,
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SC520_ISA_MEM_BUS,
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SC520_ISA_MEM_PHYS,
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SC520_ISA_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 3,
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SC520_PCI_IO_BUS,
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SC520_PCI_IO_PHYS,
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SC520_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* ISA/PCI I/O space */
|
||||
pci_set_region(hose->regions + 4,
|
||||
SC520_ISA_IO_BUS,
|
||||
SC520_ISA_IO_PHYS,
|
||||
SC520_ISA_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 5;
|
||||
|
||||
pci_setup_type1(hose,
|
||||
SC520_REG_ADDR,
|
||||
SC520_REG_DATA);
|
||||
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
|
||||
/* enable target memory acceses on host brige */
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* stuff specific for the sc520, but independent of implementation */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ic/ssi.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
|
||||
{
|
||||
u8 temp=0;
|
||||
|
||||
if (freq >= 8192) {
|
||||
temp |= CTL_CLK_SEL_4;
|
||||
} else if (freq >= 4096) {
|
||||
temp |= CTL_CLK_SEL_8;
|
||||
} else if (freq >= 2048) {
|
||||
temp |= CTL_CLK_SEL_16;
|
||||
} else if (freq >= 1024) {
|
||||
temp |= CTL_CLK_SEL_32;
|
||||
} else if (freq >= 512) {
|
||||
temp |= CTL_CLK_SEL_64;
|
||||
} else if (freq >= 256) {
|
||||
temp |= CTL_CLK_SEL_128;
|
||||
} else if (freq >= 128) {
|
||||
temp |= CTL_CLK_SEL_256;
|
||||
} else {
|
||||
temp |= CTL_CLK_SEL_512;
|
||||
}
|
||||
|
||||
if (!lsb_first) {
|
||||
temp |= MSBF_ENB;
|
||||
}
|
||||
|
||||
if (inv_clock) {
|
||||
temp |= CLK_INV_ENB;
|
||||
}
|
||||
|
||||
if (inv_phase) {
|
||||
temp |= PHS_INV_ENB;
|
||||
}
|
||||
|
||||
write_mmcr_byte(SC520_SSICTL, temp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 ssi_txrx_byte(u8 data)
|
||||
{
|
||||
write_mmcr_byte(SC520_SSIXMIT, data);
|
||||
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
|
||||
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
|
||||
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
|
||||
return read_mmcr_byte(SC520_SSIRCV);
|
||||
}
|
||||
|
||||
|
||||
void ssi_tx_byte(u8 data)
|
||||
{
|
||||
write_mmcr_byte(SC520_SSIXMIT, data);
|
||||
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
|
||||
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
|
||||
}
|
||||
|
||||
u8 ssi_rx_byte(void)
|
||||
{
|
||||
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
|
||||
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
|
||||
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
|
||||
return read_mmcr_byte(SC520_SSIRCV);
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* stuff specific for the sc520, but independent of implementation */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <asm/ic/sc520.h>
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
write_mmcr_word(SC520_GPTMR0CNT, 0);
|
||||
write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
|
||||
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
/* fixme: 30 or 33 */
|
||||
return read_mmcr_word(SC520_GPTMR0CNT) / 33;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
/* FixMe: use two cascade coupled timers */
|
||||
write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
|
||||
write_mmcr_word(SC520_GPTMR0CNT, t*33);
|
||||
write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
|
||||
}
|
||||
|
||||
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
int m=0;
|
||||
long u;
|
||||
|
||||
read_mmcr_word(SC520_SWTMRMILLI);
|
||||
read_mmcr_word(SC520_SWTMRMICRO);
|
||||
|
||||
#if 0
|
||||
/* do not enable this line, udelay is used in the serial driver -> recursion */
|
||||
printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
|
||||
#endif
|
||||
while (1) {
|
||||
|
||||
m += read_mmcr_word(SC520_SWTMRMILLI);
|
||||
u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
|
||||
|
||||
if (usec <= u) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue