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ppc/8xxx: Misc DDR related fixes 

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-09-10 14:54:55 -05:00
parent 3e3c9c157b
commit 6d8565a1ed
2 changed files with 7 additions and 7 deletions
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8
cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2008 Freescale Semiconductor, Inc. * Copyright 2008-2009 Freescale Semiconductor, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
@ -675,10 +675,10 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
esdmode = (0 esdmode = (0
| ((qoff & 0x1) << 12) | ((qoff & 0x1) << 12)
| ((tdqs_en & 0x1) << 11) | ((tdqs_en & 0x1) << 11)
| ((rtt & 0x4) << 9) /* rtt field is split */ | ((rtt & 0x4) << 7) /* rtt field is split */
| ((wrlvl_en & 0x1) << 7) | ((wrlvl_en & 0x1) << 7)
| ((rtt & 0x2) << 6) /* rtt field is split */ | ((rtt & 0x2) << 5) /* rtt field is split */
| ((dic & 0x2) << 5) /* DIC field is split */ | ((dic & 0x2) << 4) /* DIC field is split */
| ((al & 0x3) << 3) | ((al & 0x3) << 3)
| ((rtt & 0x1) << 2) /* rtt field is split */ | ((rtt & 0x1) << 2) /* rtt field is split */
| ((dic & 0x1) << 1) /* DIC field is split */ | ((dic & 0x1) << 1) /* DIC field is split */

4
cpu/mpc8xxx/ddr/ddr3_dimm_params.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2008 Freescale Semiconductor, Inc. * Copyright 2008-2009 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com> * Dave Liu <daveliu@freescale.com>
* *
* calculate the organization and timing parameter * calculate the organization and timing parameter
@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
bsize = 1ULL << (nbit_sdram_cap_bsize - 3 bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width); + nbit_primary_bus_width - nbit_sdram_width);
debug("DDR: DDR III rank density = 0x%08x\n", bsize); debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
return bsize; return bsize;
} }