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arm: dts: mediatek: add ethernet and sgmii dts node for mt7622 

This patch add eth and sgmii dts node for mt7622 to support ethernet

Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
This commit is contained in:
MarkLee 2020-01-21 19:31:59 +08:00 committed by Tom Rini
parent e395717ca9
commit 6efa450565
2 changed files with 58 additions and 0 deletions
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13
arch/arm/dts/mt7622-rfb.dts
View File

@ -178,3 +178,16 @@
pinctrl-0 = <&watchdog_pins>; pinctrl-0 = <&watchdog_pins>;
status = "okay"; status = "okay";
}; };
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};

45
arch/arm/dts/mt7622.dtsi
View File

@ -7,6 +7,9 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h> #include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/gpio/gpio.h>
/ { / {
compatible = "mediatek,mt7622"; compatible = "mediatek,mt7622";
@ -182,4 +185,46 @@
clock-names = "source", "hclk"; clock-names = "source", "hclk";
status = "disabled"; status = "disabled";
}; };
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth", "syscon";
reg = <0x1b100000 0x20000>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&ethsys CLK_ETH_ESW_EN>,
<&ethsys CLK_ETH_GP0_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&sgmiisys CLK_SGMII_TX250M_EN>,
<&sgmiisys CLK_SGMII_RX250M_EN>,
<&sgmiisys CLK_SGMII_CDR_REF>,
<&sgmiisys CLK_SGMII_CDR_FB>,
<&topckgen CLK_TOP_SGMIIPLL>,
<&apmixedsys CLK_APMIXED_ETH2PLL>;
clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
"eth2pll";
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
resets = <&ethsys ETHSYS_FE_RST>;
reset-names = "fe";
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sgmiisys: sgmiisys@1b128000 {
compatible = "mediatek,mt7622-sgmiisys", "syscon";
reg = <0x1b128000 0x3000>;
#clock-cells = <1>;
};
}; };