LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw25: fix io pin muxing for 2nd ethernet rmii

This commit is contained in:
Rene Straub 2020-11-27 19:49:23 +01:00
parent e85e9ffa83
commit 6f10e899b1
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
board/nm/hw25/board.c
View File

@ -110,6 +110,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define DDR3_CLOCK_FREQUENCY (400)
#define REG_CONTROL_MODULE_SMA2 (CTRL_BASE + 0x0001320)
#define REG_CONTROL_MODULE_SMA2_RMII2_CRS_DV_MODE_SEL (0x00000001)
#if !defined(CONFIG_SPL_BUILD)
/* Hardware version information of mainboard, loaded by get_hw_version() */
@ -1130,6 +1133,13 @@ int board_eth_init(bd_t *bis)
cpsw_data.mdio_div = 0x3E;
/* The RMII2_CRS_DV on GPMC_A9 can also be used as MMC2_DAT7.
For both functions the pin must be in pinmux mode 3.
The default function is MMC2_DAT7, therefore we need to
change it to RMII2_CRS_DV using a secondary pinmux
that is controlled via control module register sma2. */
writel(REG_CONTROL_MODULE_SMA2_RMII2_CRS_DV_MODE_SEL, REG_CONTROL_MODULE_SMA2);
bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
set_mac_address(0, mac_addr0);