powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Christophe Leroy
Tom Rini
parent
73bc94c6b7
commit
70fd071001
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@ -73,12 +73,15 @@ static int check_CPU (long clock, uint pvr, uint immr)
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id_str =
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"PC866x"; /* Unknown chip from MPC866 family */
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break;
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case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
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case 0x09000000:
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pre = 'M'; mid = suf = ""; m = 1;
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if (id_str == NULL)
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id_str = "PC885"; /* 870/875/880/885 */
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break;
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default: suf = NULL; break;
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default:
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suf = NULL;
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break;
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}
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if (id_str == NULL)
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@ -99,9 +102,8 @@ static int check_CPU (long clock, uint pvr, uint immr)
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if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
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printf(" FEC present");
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if (!m) {
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if (!m)
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puts(cpu_warning);
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}
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putc('\n');
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@ -239,9 +241,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
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* - sizeof (ulong) is usually a valid address. Better pick an address
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* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
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* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
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* Better pick an address known to be invalid on your system and assign
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* it to CONFIG_SYS_RESET_ADDRESS.
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* "(ulong)-1" used to be a good choice for many systems...
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*/
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addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
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@ -264,7 +267,7 @@ unsigned long get_tbclk (void)
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ulong oscclk, factor, pll;
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if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
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return (gd->cpu_clk / 16);
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return gd->cpu_clk / 16;
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pll = in_be32(&immap->im_clkrst.car_plprcr);
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@ -288,9 +291,9 @@ unsigned long get_tbclk (void)
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if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
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factor > 2)
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return (oscclk / 4);
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return oscclk / 4;
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return (oscclk / 16);
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return oscclk / 16;
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}
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/* ------------------------------------------------------------------------- */
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@ -184,5 +184,5 @@ void cpu_init_f(immap_t __iomem *immr)
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*/
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int cpu_init_r(void)
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{
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return (0);
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return 0;
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}
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@ -102,7 +102,7 @@ static struct ether_fcc_info_s
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#define PKT_MAXBLR_SIZE 1520
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#ifdef __GNUC__
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static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
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static char txbuf[DBUF_LENGTH] __aligned(8);
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#else
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#error txbuf must be aligned.
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#endif
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@ -138,7 +138,6 @@ int fec_initialize(bd_t *bis)
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int i;
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for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
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dev = malloc(sizeof(*dev));
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if (dev == NULL)
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hang();
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@ -147,12 +146,11 @@ int fec_initialize(bd_t *bis)
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/* for FEC1 make sure that the name of the interface is the same
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as the old one for compatibility reasons */
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if (i == 0) {
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if (i == 0)
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strcpy(dev->name, "FEC");
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} else {
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else
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sprintf(dev->name, "FEC%d",
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ether_fcc_info[i].ether_index + 1);
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}
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efis = ðer_fcc_info[i];
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@ -202,9 +200,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
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udelay(1);
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j++;
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}
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if (j>=TOUT_LOOP) {
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if (j >= TOUT_LOOP)
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printf("TX not ready\n");
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}
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out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
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out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
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@ -221,9 +218,9 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
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udelay(1);
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j++;
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}
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if (j>=TOUT_LOOP) {
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if (j >= TOUT_LOOP)
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printf("TX timeout\n");
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}
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/* return only status bits */;
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rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
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@ -436,7 +433,6 @@ static void fec_pin_init(int fecidx)
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#endif /* CONFIG_ETHER_ON_FEC1 */
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} else if (fecidx == 1) {
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#if defined(CONFIG_ETHER_ON_FEC2)
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#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
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@ -467,7 +463,6 @@ static void fec_pin_init(int fecidx)
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#endif /* CONFIG_MPC885_FAMILY */
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#endif /* CONFIG_ETHER_ON_FEC2 */
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}
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}
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@ -554,7 +549,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
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/*
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* Setup Buffers and Buffer Desriptors
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* Setup Buffers and Buffer Descriptors
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*/
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rxIdx = 0;
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txIdx = 0;
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@ -636,22 +631,20 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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/*
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* adapt the RMII speed to the speed of the phy
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*/
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if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
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if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
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fec_100Mbps(dev);
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} else {
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else
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fec_10Mbps(dev);
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}
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#endif
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#if defined(CONFIG_MII)
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/*
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* adapt to the half/full speed settings
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*/
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if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
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if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
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fec_full_duplex(dev);
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} else {
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else
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fec_half_duplex(dev);
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}
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#endif
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/* And last, try to fill Rx Buffer Descriptors */
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@ -744,7 +737,7 @@ mii_send(uint mii_cmd)
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}
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mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
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out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
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return (mii_reply & 0xffff); /* data read from phy */
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return mii_reply & 0xffff; /* data read from phy */
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}
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#endif
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@ -776,9 +769,9 @@ static int mii_discover_phy(struct eth_device *dev)
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}
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}
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}
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if (phyaddr < 0) {
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if (phyaddr < 0)
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printf("No PHY device found.\n");
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}
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return phyaddr;
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}
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#endif /* CONFIG_SYS_DISCOVER_PHY */
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@ -19,8 +19,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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int
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do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
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@ -37,8 +36,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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return 0;
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}
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int
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do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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@ -60,8 +58,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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return 0;
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}
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int
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do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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car8xx_t __iomem *car = &immap->im_clkrst;
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@ -74,8 +71,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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static int counter;
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static void
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header(void)
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static void header(void)
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{
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char *data = "\
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-------------------------------- --------------------------------\
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@ -123,8 +119,7 @@ static void binary (char *label, uint value, int nbits)
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#define PC_NBITS 12
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#define PD_NBITS 13
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int
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do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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iop8xx_t __iomem *iop = &immap->im_ioport;
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@ -177,14 +172,13 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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* this needs a clean up for smaller tighter code
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* use *uint and set the address based on cmd + port
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*/
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int
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do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint rcode = 0;
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iopin_t iopin;
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static uint port = 0;
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static uint pin = 0;
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static uint value = 0;
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static uint port;
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static uint pin;
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static uint value;
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static enum {
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DIR,
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PAR,
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@ -281,7 +275,6 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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iopin_set_anyedge(&iopin);
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break;
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}
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}
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return rcode;
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}
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@ -335,8 +328,7 @@ static void prbrg (int n, uint val)
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putc('\n');
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}
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int
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do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immap->im_cpm;
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@ -42,7 +42,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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/* Configure CPM interrupts */
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cpm_interrupt_init();
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return (0);
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return 0;
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}
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/************************************************************************/
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@ -146,30 +146,24 @@ static void cpm_error_interrupt (void *dummy)
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/*
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* Install and free an interrupt handler
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*/
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void irq_install_handler (int vec, interrupt_handler_t * handler,
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void *arg)
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void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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if ((vec & CPMVEC_OFFSET) != 0) {
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/* CPM interrupt */
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vec &= 0xffff;
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if (cpm_vecs[vec].handler != NULL) {
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if (cpm_vecs[vec].handler != NULL)
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printf("CPM interrupt 0x%x replacing 0x%x\n",
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(uint) handler,
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(uint) cpm_vecs[vec].handler);
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}
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(uint)handler, (uint)cpm_vecs[vec].handler);
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cpm_vecs[vec].handler = handler;
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cpm_vecs[vec].arg = arg;
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setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
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} else {
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/* SIU interrupt */
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if (irq_vecs[vec].handler != NULL) {
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if (irq_vecs[vec].handler != NULL)
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printf("SIU interrupt %d 0x%x replacing 0x%x\n",
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vec,
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(uint) handler,
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(uint) cpm_vecs[vec].handler);
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}
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vec, (uint)handler, (uint)cpm_vecs[vec].handler);
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irq_vecs[vec].handler = handler;
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irq_vecs[vec].arg = arg;
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setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
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@ -185,11 +185,10 @@ static int smc_init (void)
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/* Enable transmitter/receiver. */
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setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
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return (0);
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return 0;
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}
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static void
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smc_putc(const char c)
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static void smc_putc(const char c)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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@ -209,16 +208,13 @@ smc_putc(const char c)
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WATCHDOG_RESET();
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}
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static void
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smc_puts (const char *s)
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static void smc_puts(const char *s)
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{
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while (*s) {
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while (*s)
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smc_putc(*s++);
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}
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}
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static int
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smc_getc(void)
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static int smc_getc(void)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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@ -245,11 +241,10 @@ smc_getc(void)
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setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
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}
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out_be32(&rtx->rxindex, rxindex);
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return(c);
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return c;
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}
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static int
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smc_tstc(void)
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static int smc_tstc(void)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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@ -260,8 +255,7 @@ smc_tstc(void)
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return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
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}
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struct serial_device serial_smc_device =
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{
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struct serial_device serial_smc_device = {
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.name = "serial_smc",
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.start = smc_init,
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.stop = NULL,
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@ -59,5 +59,5 @@ int get_clocks (void)
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get_brgclk(sccr);
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return (0);
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return 0;
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}
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@ -50,10 +50,6 @@
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/* -------------------
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* Function prototypes
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* ------------------- */
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void spi_init (void);
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ssize_t spi_read (uchar *, int, uchar *, int);
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ssize_t spi_write (uchar *, int, uchar *, int);
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ssize_t spi_xfer(size_t);
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/* -------------------
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@ -120,7 +116,7 @@ void spi_init_f (void)
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* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
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* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
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* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
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* PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
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* PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
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* ---------------------------------------------- */
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clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
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@ -253,14 +249,12 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
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*txbuf = SPI_EEPROM_RDSR; /* read status */
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txbuf[1] = 0;
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||||
spi_xfer(2);
|
||||
if (!(rxbuf[1] & 1)) {
|
||||
if (!(rxbuf[1] & 1))
|
||||
break;
|
||||
}
|
||||
udelay(1000);
|
||||
}
|
||||
if (i >= 1000) {
|
||||
if (i >= 1000)
|
||||
printf("*** spi_write: Time out while writing!\n");
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
|
@ -334,9 +328,8 @@ ssize_t spi_xfer (size_t count)
|
|||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
if (tm >= 1000) {
|
||||
if (tm >= 1000)
|
||||
printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
|
||||
}
|
||||
|
||||
/* Clear CS for device */
|
||||
setbits_be32(&cp->cp_pbdat, 0x0001);
|
||||
|
|
|
|||
|
|
@ -45,7 +45,8 @@ static void print_backtrace(unsigned long *sp)
|
|||
if (cnt++ % 7 == 0)
|
||||
printf("\n");
|
||||
printf("%08lX ", i);
|
||||
if (cnt > 32) break;
|
||||
if (cnt > 32)
|
||||
break;
|
||||
sp = (unsigned long *)*sp;
|
||||
}
|
||||
printf("\n");
|
||||
|
|
@ -58,25 +59,21 @@ void show_regs(struct pt_regs *regs)
|
|||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
|
||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
|
||||
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
|
||||
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
|
||||
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
|
||||
regs->msr&MSR_IR ? 1 : 0,
|
||||
regs->msr, regs->msr & MSR_EE ? 1 : 0,
|
||||
regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
|
||||
regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
|
||||
regs->msr & MSR_DR ? 1 : 0);
|
||||
|
||||
printf("\n");
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i % 8) == 0)
|
||||
{
|
||||
printf("GPR%02d: ", i);
|
||||
}
|
||||
|
||||
printf("%08lX ", regs->gpr[i]);
|
||||
if ((i % 8) == 7)
|
||||
{
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void _exception(int signr, struct pt_regs *regs)
|
||||
|
|
@ -88,13 +85,13 @@ static void _exception(int signr, struct pt_regs *regs)
|
|||
|
||||
void MachineCheckException(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long fixup;
|
||||
unsigned long fixup = search_exception_table(regs->nip);
|
||||
|
||||
/* Probing PCI using config cycles cause this exception
|
||||
* when a device is not present. Catch it and return to
|
||||
* the PCI exception handler.
|
||||
*/
|
||||
if ((fixup = search_exception_table(regs->nip)) != 0) {
|
||||
if (fixup != 0) {
|
||||
regs->nip = fixup;
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,8 +27,7 @@ typedef struct {
|
|||
#define IOPIN_PORTC 2
|
||||
#define IOPIN_PORTD 3
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_high(iopin_t *iopin)
|
||||
static inline void iopin_set_high(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -51,8 +50,7 @@ iopin_set_high(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_low(iopin_t *iopin)
|
||||
static inline void iopin_set_low(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -75,8 +73,7 @@ iopin_set_low(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_high(iopin_t *iopin)
|
||||
static inline uint iopin_is_high(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -100,8 +97,7 @@ iopin_is_high(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_low(iopin_t *iopin)
|
||||
static inline uint iopin_is_low(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -125,8 +121,7 @@ iopin_is_low(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_out(iopin_t *iopin)
|
||||
static inline void iopin_set_out(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -149,8 +144,7 @@ iopin_set_out(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_in(iopin_t *iopin)
|
||||
static inline void iopin_set_in(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -173,8 +167,7 @@ iopin_set_in(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_out(iopin_t *iopin)
|
||||
static inline uint iopin_is_out(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -198,8 +191,7 @@ iopin_is_out(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_in(iopin_t *iopin)
|
||||
static inline uint iopin_is_in(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -223,8 +215,7 @@ iopin_is_in(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_odr(iopin_t *iopin)
|
||||
static inline void iopin_set_odr(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -239,8 +230,7 @@ iopin_set_odr(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_act(iopin_t *iopin)
|
||||
static inline void iopin_set_act(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -255,8 +245,7 @@ iopin_set_act(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_odr(iopin_t *iopin)
|
||||
static inline uint iopin_is_odr(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -272,8 +261,7 @@ iopin_is_odr(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_act(iopin_t *iopin)
|
||||
static inline uint iopin_is_act(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -289,8 +277,7 @@ iopin_is_act(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_ded(iopin_t *iopin)
|
||||
static inline void iopin_set_ded(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -313,8 +300,7 @@ iopin_set_ded(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_gen(iopin_t *iopin)
|
||||
static inline void iopin_set_gen(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -337,8 +323,7 @@ iopin_set_gen(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_ded(iopin_t *iopin)
|
||||
static inline uint iopin_is_ded(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -362,8 +347,7 @@ iopin_is_ded(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_gen(iopin_t *iopin)
|
||||
static inline uint iopin_is_gen(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -387,8 +371,7 @@ iopin_is_gen(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_opt2(iopin_t *iopin)
|
||||
static inline void iopin_set_opt2(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -399,8 +382,7 @@ iopin_set_opt2(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_opt1(iopin_t *iopin)
|
||||
static inline void iopin_set_opt1(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -411,8 +393,7 @@ iopin_set_opt1(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_opt2(iopin_t *iopin)
|
||||
static inline uint iopin_is_opt2(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -424,8 +405,7 @@ iopin_is_opt2(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_opt1(iopin_t *iopin)
|
||||
static inline uint iopin_is_opt1(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -437,8 +417,7 @@ iopin_is_opt1(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_falledge(iopin_t *iopin)
|
||||
static inline void iopin_set_falledge(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -449,8 +428,7 @@ iopin_set_falledge(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
iopin_set_anyedge(iopin_t *iopin)
|
||||
static inline void iopin_set_anyedge(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -461,8 +439,7 @@ iopin_set_anyedge(iopin_t *iopin)
|
|||
}
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_falledge(iopin_t *iopin)
|
||||
static inline uint iopin_is_falledge(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
@ -474,8 +451,7 @@ iopin_is_falledge(iopin_t *iopin)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ uint
|
||||
iopin_is_anyedge(iopin_t *iopin)
|
||||
static inline uint iopin_is_anyedge(iopin_t *iopin)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* This file contains structures and information for the communication
|
||||
* processor channels. Some CPM control and status is available
|
||||
* throught the MPC8xx internal memory map. See immap.h for details.
|
||||
* through the MPC8xx internal memory map. See immap.h for details.
|
||||
* This file only contains what I need for the moment, not the total
|
||||
* CPM capabilities. I (or someone else) will add definitions as they
|
||||
* are needed. -- Dan
|
||||
|
|
@ -81,7 +81,7 @@ typedef struct cpm_buf_desc {
|
|||
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
|
||||
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
|
||||
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
|
||||
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
|
||||
#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
|
||||
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
|
||||
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
|
||||
#define BD_SC_BR ((ushort)0x0020) /* Break received */
|
||||
|
|
@ -672,7 +672,7 @@ typedef struct hdlc_pram_s {
|
|||
#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
|
||||
#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
|
||||
|
||||
extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
|
||||
void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
|
||||
|
||||
/* CPM interrupt configuration vector.
|
||||
*/
|
||||
|
|
@ -680,7 +680,7 @@ extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
|
|||
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
|
||||
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
|
||||
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
|
||||
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
|
||||
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
|
||||
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
|
||||
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
|
||||
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
|
||||
|
|
|
|||
Loading…
Reference in New Issue