ARM: zynq: Support systems with more memory banks
This is example how to change u-boot to support more memory banks read from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Michal Simek
parent
c1584e2a21
commit
758f29d0f8
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@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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/*
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* fdt_get_reg - Fill buffer by information from DT
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*/
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static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
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const u32 *cell, int n)
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{
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int i = 0, b, banks;
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int parent_offset = fdt_parent_offset(fdt, nodeoffset);
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int address_cells = fdt_address_cells(fdt, parent_offset);
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int size_cells = fdt_size_cells(fdt, parent_offset);
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char *p = buf;
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u64 val;
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u64 vals;
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debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
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__func__, address_cells, size_cells, buf, cell);
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/* Check memory bank setup */
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banks = n % (address_cells + size_cells);
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if (banks)
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panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
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n, address_cells, size_cells);
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banks = n / (address_cells + size_cells);
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for (b = 0; b < banks; b++) {
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debug("%s: Bank #%d:\n", __func__, b);
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if (address_cells == 2) {
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val = cell[i + 1];
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val <<= 32;
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val |= cell[i];
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val = fdt64_to_cpu(val);
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debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
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__func__, val, p, &cell[i]);
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*(phys_addr_t *)p = val;
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} else {
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debug("%s: addr32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_addr_t);
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i += address_cells;
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debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
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sizeof(phys_addr_t));
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if (size_cells == 2) {
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vals = cell[i + 1];
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vals <<= 32;
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vals |= cell[i];
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vals = fdt64_to_cpu(vals);
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debug("%s: size64=%llx, ptr=%p, cell=%p\n",
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__func__, vals, p, &cell[i]);
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*(phys_size_t *)p = vals;
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} else {
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debug("%s: size32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_size_t);
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i += size_cells;
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debug("%s: ps=%p, i=%x, size=%zu\n",
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__func__, p, i, sizeof(phys_size_t));
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}
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/* Return the first address size */
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return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
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}
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#define FDT_REG_SIZE sizeof(u32)
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/* Temp location for sharing data for storing */
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/* Up to 64-bit address + 64-bit size */
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static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
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void dram_init_banksize(void)
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{
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int bank;
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memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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debug("Bank #%d: start %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].start);
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debug("Bank #%d: size %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].size);
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}
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}
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int dram_init(void)
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{
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int node;
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fdt_addr_t addr;
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fdt_size_t size;
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int node, len;
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const void *blob = gd->fdt_blob;
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const u32 *cell;
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node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
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"memory", 7);
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if (node == -FDT_ERR_NOTFOUND) {
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debug("ZYNQ DRAM: Can't get memory node\n");
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memset(&tmp, 0, sizeof(tmp));
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/* find or create "/memory" node. */
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node = fdt_subnode_offset(blob, 0, "memory");
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if (node < 0) {
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printf("%s: Can't get memory node\n", __func__);
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return node;
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}
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/* Get pointer to cells and lenght of it */
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell) {
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printf("%s: Can't get reg property\n", __func__);
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return -1;
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}
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addr = fdtdec_get_addr_size(blob, node, "reg", &size);
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if (addr == FDT_ADDR_T_NONE || size == 0) {
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debug("ZYNQ DRAM: Can't get base address or size\n");
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return -1;
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}
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gd->ram_size = size;
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gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
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debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
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zynq_ddrc_init();
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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zynq_ddrc_init();
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return 0;
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}
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#endif
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@ -277,7 +277,9 @@
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/* Physical Memory map */
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#define CONFIG_SYS_TEXT_BASE 0x4000000
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#define CONFIG_NR_DRAM_BANKS 1
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#ifndef CONFIG_NR_DRAM_BANKS
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# define CONFIG_NR_DRAM_BANKS 1
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#endif
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#define CONFIG_SYS_MEMTEST_START 0
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#define CONFIG_SYS_MEMTEST_END 0x1000
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