hancock: quirk for ethernet PHY reset
- implement 2nd ethernet reset to properly pinstrap ethernet PHY after Ethernet switch is booted.
This commit is contained in:
Rene Straub
Patrick Zysset
parent
68329cfb6d
commit
75cf0fdbbb
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@ -391,8 +391,6 @@ void am33xx_spl_board_init(void)
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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printf("Console: %d\n", CONFIG_CONS_INDEX);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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@ -439,10 +437,60 @@ static void init_ethernet(void)
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REQUEST_AND_CLEAR_GPIO(GPIO_RST_ETH_N);
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/* Minimum Reset Pulse = 5us (switch), 20us (TJA1100), 100us (SMSC8720) */
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mdelay(1);
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/* TODO: Release reset */
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gpio_set_value(GPIO_RST_ETH_N, 1);
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}
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static void init_ethernet_switch(void)
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{
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uint32_t val;
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if (spi == 0) {
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configure_module_pin_mux(spi1_pin_mux);
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/* TODO: Check whether bitrate can be increased to 5..10MHz */
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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/* spi_set_wordlen(spi,32);*/
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}
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spi_claim_bus(spi);
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/* TODO: Remove debug printout later on */
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val = sja1105_read_reg(spi, 0x000000);
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/* printf("Device ID: %08x\n", val); */
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val = sja1105_read_reg(spi, 0x000001);
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/* printf("Status Reg: %08x\n", val); */
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sja1105_static_init(spi, 0 /*dummy*/);
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/* Check that config was properly loaded */
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val = sja1105_read_reg(spi, 0x000001);
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/* printf("Status Reg: %08x\n", val); */
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if ((val & 0x80000000) != 0x80000000) {
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printf("ERROR: Switch configuration load failed\n");
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}
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/* Configure clocks */
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sja1105_dynamic_init(spi);
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/*
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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*/
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/* Enable pull down on CPU Port RX_ER etc. */
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sja1105_write_reg(spi, 0x100809, 0x03020313);
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#if 0
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val = sja1105_read_reg(spi, 0x100809);
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printf("CFG_PAD_MII4_RX Reg: %08x\n", val);
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#endif
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spi_release_bus(spi);
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}
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static void init_usb_hub(void)
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{
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REQUEST_AND_CLEAR_GPIO(GPIO_RST_USB_HUB_N);
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@ -474,7 +522,6 @@ static void init_user_module(void)
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puts("ready\n");
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}
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static void init_gsm(void)
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{
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/*
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@ -523,56 +570,6 @@ static void init_gnss(void)
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REQUEST_AND_SET_GPIO(GPIO_RST_GNSS);
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}
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static void init_ethernet_switch(void)
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{
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uint32_t val;
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if (spi == 0) {
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configure_module_pin_mux(spi1_pin_mux);
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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/* spi_set_wordlen(spi,32);*/
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}
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spi_claim_bus(spi);
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/* TODO: Remove debug printout later on */
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val = sja1105_read_reg(spi, 0x000000);
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/* printf("Device ID: %08x\n", val); */
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val = sja1105_read_reg(spi, 0x000001);
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/* printf("Status Reg: %08x\n", val); */
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sja1105_static_init(spi, 0 /*dummy*/);
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/* Check that config was properly loaded */
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val = sja1105_read_reg(spi, 0x000001);
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/* printf("Status Reg: %08x\n", val); */
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if ((val & 0x80000000) != 0x80000000) {
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printf("ERROR: Switch configuration load failed\n");
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}
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/* Configure clocks */
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sja1105_dynamic_init(spi);
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/*
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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*/
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/* Enable pull down on CPU Port RX_ER etc. */
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sja1105_write_reg(spi, 0x100809, 0x03020313);
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#if 0
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val = sja1105_read_reg(spi, 0x100809);
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printf("CFG_PAD_MII4_RX Reg: %08x\n", val);
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#endif
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spi_release_bus(spi);
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}
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#endif /* !defined(CONFIG_SPL_BUILD) */
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@ -608,43 +605,16 @@ int board_init(void)
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#if !defined(CONFIG_SPL_BUILD)
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// TODO: Check tty logic with NRSW team
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// UART1: Fixed to mains connector, always present
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// UART0: Mapped to shield slot
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// Can only be used when shield is installed
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void set_console(void)
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{
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const char *defaultconsole = getenv("defaultconsole");
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if (defaultconsole == 0) {
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/* Use the default console */
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setenv("defaultconsole", "ttyS1");
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setenv("defaultconsole", "ttyS2");
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}
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#if 0
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/* Don't allow changing to ttyS0 because ttyS0 is not available in the
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* kernel if no comio shield is available */
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if (shield_id != SHIELD_COM_IO) {
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return;
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}
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/* With comio shield the defaultconsole should be ttyS0 and not ttyS1 */
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setenv("defaultconsole", "ttyS0");
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/* If consoledev is set, take this as productive console instead of default console */
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if (read_file("/root/boot/consoledev", buf, 5) != 5) {
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puts("Invalid file consoledev\n");
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return;
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}
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if (strstr(buf, "tty")==buf) {
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buf[5] = 0;
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setenv("defaultconsole", buf);
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}
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#endif
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}
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#if 0
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static void set_devicetree_name(void)
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{
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char devicetreename[64];
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@ -679,7 +649,7 @@ static void get_hw_version(void)
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char new_env[256]; /* current bootargs = 84 bytes */
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bd_get_hw_version(&hw_ver, &hw_rev);
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printf("Hank: V%d.%d\n", hw_ver, hw_rev);
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printf("MB: V%d.%d\n", hw_ver, hw_rev);
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/* add hardware versions to environment */
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snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
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@ -687,6 +657,18 @@ static void get_hw_version(void)
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setenv("add_version_bootargs", new_env);
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}
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static void get_pmic_version(void)
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{
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uint8_t val = 0x00;
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uint8_t ver, rev;
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da9063_get_reg(PMIC_REG_CONFIG_ID, &val);
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ver = (val >> 4) & 0xF;
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rev = (val >> 0) & 0xF;
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printf("PMIC: V%d.%d\n", ver, rev);
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}
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#if 0
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static void check_fct(void)
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{
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/* Check whether an I2C device (EEPROM) is present at address 0xA2/0x51
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@ -738,7 +720,7 @@ static void check_reset_button(void)
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if (!get_button_state())
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break;
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2 udelay(100*1000); /* 100ms */
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udelay(100*1000); /* 100ms */
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counter += 100;
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if (counter == 2000) {
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@ -791,14 +773,13 @@ static void check_reset_button(void)
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int board_late_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD)
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/*
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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get_hw_version();
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get_pmic_version();
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set_root_partition();
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set_devicetree_name();
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*/
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/* Initialize pins */
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REQUEST_AND_CLEAR_GPIO(GPIO_WLAN_EN);
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@ -810,7 +791,22 @@ int board_late_init(void)
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REQUEST_AND_CLEAR_GPIO(GPIO_SIM_SEL);
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REQUEST_AND_CLEAR_GPIO(GPIO_RST_UI_N);
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/* FIXME: Problem switch reset lines of switch and PHY
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* Clocks for PHY are only present once switch is configured
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* Thus need to repeat reset sequence once in order to have
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* PHY also properly bootstrapped.
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* Should be reworked by giving switch a dedicated reset line
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*/
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init_ethernet();
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init_ethernet_switch();
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/* FIXME: Reset ETH system again to pin strap PHY */
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mdelay(10);
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gpio_set_value(GPIO_RST_ETH_N, 0);
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mdelay(10);
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gpio_set_value(GPIO_RST_ETH_N, 1);
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init_ethernet_switch();
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init_usb_hub();
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init_user_module();
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init_gsm();
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@ -833,9 +829,6 @@ int board_late_init(void)
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check_fct();
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*/
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init_ethernet_switch();
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#endif
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return 0;
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@ -963,91 +956,6 @@ int board_fit_config_name_match(const char *name)
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#if !defined(CONFIG_SPL_BUILD)
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static int do_spitest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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/* const uint8_t data[] = { 0xFF, 0xAA, 0x00 };*/
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const uint8_t data[] = { 0xAA, 0x55, 0xAA, 0x55, 0x00, 0xFF };
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int rc;
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printf("SPI test\n");
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if (spi == 0) {
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/* printf("SPI1.CS Mux %08x\n", readl(0x44e10964)); */
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configure_module_pin_mux(spi1_pin_mux);
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/* printf("SPI1.CS Mux %08x\n", readl(0x44e10964)); */
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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}
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printf("SPI Driver: %p\n", spi);
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spi_claim_bus(spi);
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rc = spi_xfer(spi, 8*sizeof(data) /*bitlen*/, data, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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printf("spi_xfer %d\n", rc);
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spi_release_bus(spi);
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return 0;
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}
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U_BOOT_CMD(
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spitest, 1, 1, do_spitest,
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"spi test function",
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""
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);
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static int do_sjastart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint32_t val;
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if (spi == 0) {
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configure_module_pin_mux(spi1_pin_mux);
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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/* spi_set_wordlen(spi,32);*/
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}
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spi_claim_bus(spi);
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val = sja1105_read_reg(spi, 0x000000);
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printf("Device ID: %08x\n", val);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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sja1105_static_init(spi, 0 /*dummy*/);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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sja1105_dynamic_init(spi);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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spi_release_bus(spi);
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return 0;
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}
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U_BOOT_CMD(
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sjastart, 1, 1, do_sjastart,
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"start and configure ETH switch",
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""
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);
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static int do_sjainfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint32_t p3_mac_stat;
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