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arm: spear: Purely cosmetic changes in start.S 

Before cleaning a bit further the spear/start.S file, apply a few
cosmetic changes: capital letters, comment indentation and small
rewriting.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Miquel Raynal 2019-05-07 14:18:48 +02:00 committed by Tom Rini
parent 10a5b3cd99
commit 76bdaaa196
1 changed files with 8 additions and 9 deletions
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15
arch/arm/cpu/arm926ejs/spear/start.S
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@ -31,10 +31,9 @@
.globl reset .globl reset
reset: reset:
/* /*
* SPL has to return back to BootROM in a few cases. * SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
* eg. Ethernet boot, UART boot, USB boot * UART boot, USB boot): save registers in BootROM's stack.
* Saving registers for returning back
*/ */
stmdb sp!, {r0-r12,r14} stmdb sp!, {r0-r12,r14}
bl cpu_init_crit bl cpu_init_crit
@ -52,14 +51,14 @@ reset:
*/ */
cpu_init_crit: cpu_init_crit:
/* /*
* flush v4 I/D caches * Flush v4 I/D caches
*/ */
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
/* /*
* enable instruction cache * Enable instruction cache
*/ */
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */