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rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver 

Clean the iomux definitions at grf_rk3188.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Alexander Kochetkov 2018-02-26 17:27:56 +03:00 committed by Philipp Tomsich
parent b1d093d256
commit 7a6d7d3e12
2 changed files with 380 additions and 380 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

380
arch/arm/include/asm/arch-rockchip/grf_rk3188.h
View File

@ -69,386 +69,6 @@ struct rk3188_grf {
}; };
check_member(rk3188_grf, flash_cmd_p, 0x01a4); check_member(rk3188_grf, flash_cmd_p, 0x01a4);
/* GRF_GPIO0D_IOMUX */
enum {
GPIO0D7_SHIFT = 14,
GPIO0D7_MASK = 1,
GPIO0D7_GPIO = 0,
GPIO0D7_SPI1_CSN0,
GPIO0D6_SHIFT = 12,
GPIO0D6_MASK = 1,
GPIO0D6_GPIO = 0,
GPIO0D6_SPI1_CLK,
GPIO0D5_SHIFT = 10,
GPIO0D5_MASK = 1,
GPIO0D5_GPIO = 0,
GPIO0D5_SPI1_TXD,
GPIO0D4_SHIFT = 8,
GPIO0D4_MASK = 1,
GPIO0D4_GPIO = 0,
GPIO0D4_SPI0_RXD,
GPIO0D3_SHIFT = 6,
GPIO0D3_MASK = 3,
GPIO0D3_GPIO = 0,
GPIO0D3_FLASH_CSN3,
GPIO0D3_EMMC_RSTN_OUT,
GPIO0D2_SHIFT = 4,
GPIO0D2_MASK = 3,
GPIO0D2_GPIO = 0,
GPIO0D2_FLASH_CSN2,
GPIO0D2_EMMC_CMD,
GPIO0D1_SHIFT = 2,
GPIO0D1_MASK = 1,
GPIO0D1_GPIO = 0,
GPIO0D1_FLASH_CSN1,
GPIO0D0_SHIFT = 0,
GPIO0D0_MASK = 3,
GPIO0D0_GPIO = 0,
GPIO0D0_FLASH_DQS,
GPIO0D0_EMMC_CLKOUT
};
/* GRF_GPIO1A_IOMUX */
enum {
GPIO1A7_SHIFT = 14,
GPIO1A7_MASK = 3,
GPIO1A7_GPIO = 0,
GPIO1A7_UART1_RTS_N,
GPIO1A7_SPI0_CSN0,
GPIO1A6_SHIFT = 12,
GPIO1A6_MASK = 3,
GPIO1A6_GPIO = 0,
GPIO1A6_UART1_CTS_N,
GPIO1A6_SPI0_CLK,
GPIO1A5_SHIFT = 10,
GPIO1A5_MASK = 3,
GPIO1A5_GPIO = 0,
GPIO1A5_UART1_SOUT,
GPIO1A5_SPI0_TXD,
GPIO1A4_SHIFT = 8,
GPIO1A4_MASK = 3,
GPIO1A4_GPIO = 0,
GPIO1A4_UART1_SIN,
GPIO1A4_SPI0_RXD,
GPIO1A3_SHIFT = 6,
GPIO1A3_MASK = 1,
GPIO1A3_GPIO = 0,
GPIO1A3_UART0_RTS_N,
GPIO1A2_SHIFT = 4,
GPIO1A2_MASK = 1,
GPIO1A2_GPIO = 0,
GPIO1A2_UART0_CTS_N,
GPIO1A1_SHIFT = 2,
GPIO1A1_MASK = 1,
GPIO1A1_GPIO = 0,
GPIO1A1_UART0_SOUT,
GPIO1A0_SHIFT = 0,
GPIO1A0_MASK = 1,
GPIO1A0_GPIO = 0,
GPIO1A0_UART0_SIN,
};
/* GRF_GPIO1B_IOMUX */
enum {
GPIO1B7_SHIFT = 14,
GPIO1B7_MASK = 1,
GPIO1B7_GPIO = 0,
GPIO1B7_SPI0_CSN1,
GPIO1B6_SHIFT = 12,
GPIO1B6_MASK = 3,
GPIO1B6_GPIO = 0,
GPIO1B6_SPDIF_TX,
GPIO1B6_SPI1_CSN1,
GPIO1B5_SHIFT = 10,
GPIO1B5_MASK = 3,
GPIO1B5_GPIO = 0,
GPIO1B5_UART3_RTS_N,
GPIO1B5_RESERVED,
GPIO1B4_SHIFT = 8,
GPIO1B4_MASK = 3,
GPIO1B4_GPIO = 0,
GPIO1B4_UART3_CTS_N,
GPIO1B4_GPS_RFCLK,
GPIO1B3_SHIFT = 6,
GPIO1B3_MASK = 3,
GPIO1B3_GPIO = 0,
GPIO1B3_UART3_SOUT,
GPIO1B3_GPS_SIG,
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3,
GPIO1B2_GPIO = 0,
GPIO1B2_UART3_SIN,
GPIO1B2_GPS_MAG,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3,
GPIO1B1_GPIO = 0,
GPIO1B1_UART2_SOUT,
GPIO1B1_JTAG_TDO,
GPIO1B0_SHIFT = 0,
GPIO1B0_MASK = 3,
GPIO1B0_GPIO = 0,
GPIO1B0_UART2_SIN,
GPIO1B0_JTAG_TDI,
};
/* GRF_GPIO1D_IOMUX */
enum {
GPIO1D7_SHIFT = 14,
GPIO1D7_MASK = 1,
GPIO1D7_GPIO = 0,
GPIO1D7_I2C4_SCL,
GPIO1D6_SHIFT = 12,
GPIO1D6_MASK = 1,
GPIO1D6_GPIO = 0,
GPIO1D6_I2C4_SDA,
GPIO1D5_SHIFT = 10,
GPIO1D5_MASK = 1,
GPIO1D5_GPIO = 0,
GPIO1D5_I2C2_SCL,
GPIO1D4_SHIFT = 8,
GPIO1D4_MASK = 1,
GPIO1D4_GPIO = 0,
GPIO1D4_I2C2_SDA,
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = 1,
GPIO1D3_GPIO = 0,
GPIO1D3_I2C1_SCL,
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = 1,
GPIO1D2_GPIO = 0,
GPIO1D2_I2C1_SDA,
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = 1,
GPIO1D1_GPIO = 0,
GPIO1D1_I2C0_SCL,
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = 1,
GPIO1D0_GPIO = 0,
GPIO1D0_I2C0_SDA,
};
/* GRF_GPIO3A_IOMUX */
enum {
GPIO3A7_SHIFT = 14,
GPIO3A7_MASK = 1,
GPIO3A7_GPIO = 0,
GPIO3A7_SDMMC0_DATA3,
GPIO3A6_SHIFT = 12,
GPIO3A6_MASK = 1,
GPIO3A6_GPIO = 0,
GPIO3A6_SDMMC0_DATA2,
GPIO3A5_SHIFT = 10,
GPIO3A5_MASK = 1,
GPIO3A5_GPIO = 0,
GPIO3A5_SDMMC0_DATA1,
GPIO3A4_SHIFT = 8,
GPIO3A4_MASK = 1,
GPIO3A4_GPIO = 0,
GPIO3A4_SDMMC0_DATA0,
GPIO3A3_SHIFT = 6,
GPIO3A3_MASK = 1,
GPIO3A3_GPIO = 0,
GPIO3A3_SDMMC0_CMD,
GPIO3A2_SHIFT = 4,
GPIO3A2_MASK = 1,
GPIO3A2_GPIO = 0,
GPIO3A2_SDMMC0_CLKOUT,
GPIO3A1_SHIFT = 2,
GPIO3A1_MASK = 1,
GPIO3A1_GPIO = 0,
GPIO3A1_SDMMC0_PWREN,
GPIO3A0_SHIFT = 0,
GPIO3A0_MASK = 1,
GPIO3A0_GPIO = 0,
GPIO3A0_SDMMC0_RSTN,
};
/* GRF_GPIO3B_IOMUX */
enum {
GPIO3B7_SHIFT = 14,
GPIO3B7_MASK = 3,
GPIO3B7_GPIO = 0,
GPIO3B7_CIF_DATA11,
GPIO3B7_I2C3_SCL,
GPIO3B6_SHIFT = 12,
GPIO3B6_MASK = 3,
GPIO3B6_GPIO = 0,
GPIO3B6_CIF_DATA10,
GPIO3B6_I2C3_SDA,
GPIO3B5_SHIFT = 10,
GPIO3B5_MASK = 3,
GPIO3B5_GPIO = 0,
GPIO3B5_CIF_DATA1,
GPIO3B5_HSADC_DATA9,
GPIO3B4_SHIFT = 8,
GPIO3B4_MASK = 3,
GPIO3B4_GPIO = 0,
GPIO3B4_CIF_DATA0,
GPIO3B4_HSADC_DATA8,
GPIO3B3_SHIFT = 6,
GPIO3B3_MASK = 1,
GPIO3B3_GPIO = 0,
GPIO3B3_CIF_CLKOUT,
GPIO3B2_SHIFT = 4,
GPIO3B2_MASK = 1,
GPIO3B2_GPIO = 0,
/* no muxes */
GPIO3B1_SHIFT = 2,
GPIO3B1_MASK = 1,
GPIO3B1_GPIO = 0,
GPIO3B1_SDMMC0_WRITE_PRT,
GPIO3B0_SHIFT = 0,
GPIO3B0_MASK = 1,
GPIO3B0_GPIO = 0,
GPIO3B0_SDMMC_DETECT_N,
};
/* GRF_GPIO3C_IOMUX */
enum {
GPIO3C7_SHIFT = 14,
GPIO3C7_MASK = 3,
GPIO3C7_GPIO = 0,
GPIO3C7_SDMMC1_WRITE_PRT,
GPIO3C7_RMII_CRS_DVALID,
GPIO3C7_RESERVED,
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = 3,
GPIO3C6_GPIO = 0,
GPIO3C6_SDMMC1_DECTN,
GPIO3C6_RMII_RX_ERR,
GPIO3C6_RESERVED,
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = 3,
GPIO3C5_GPIO = 0,
GPIO3C5_SDMMC1_CLKOUT,
GPIO3C5_RMII_CLKOUT,
GPIO3C5_RMII_CLKIN,
GPIO3C4_SHIFT = 8,
GPIO3C4_MASK = 3,
GPIO3C4_GPIO = 0,
GPIO3C4_SDMMC1_DATA3,
GPIO3C4_RMII_RXD1,
GPIO3C4_RESERVED,
GPIO3C3_SHIFT = 6,
GPIO3C3_MASK = 3,
GPIO3C3_GPIO = 0,
GPIO3C3_SDMMC1_DATA2,
GPIO3C3_RMII_RXD0,
GPIO3C3_RESERVED,
GPIO3C2_SHIFT = 4,
GPIO3C2_MASK = 3,
GPIO3C2_GPIO = 0,
GPIO3C2_SDMMC1_DATA1,
GPIO3C2_RMII_TXD0,
GPIO3C2_RESERVED,
GPIO3C1_SHIFT = 2,
GPIO3C1_MASK = 3,
GPIO3C1_GPIO = 0,
GPIO3C1_SDMMC1_DATA0,
GPIO3C1_RMII_TXD1,
GPIO3C1_RESERVED,
GPIO3C0_SHIFT = 0,
GPIO3C0_MASK = 3,
GPIO3C0_GPIO = 0,
GPIO3C0_SDMMC1_CMD,
GPIO3C0_RMII_TX_EN,
GPIO3C0_RESERVED,
};
/* GRF_GPIO3D_IOMUX */
enum {
GPIO3D6_SHIFT = 12,
GPIO3D6_MASK = 3,
GPIO3D6_GPIO = 0,
GPIO3D6_PWM_3,
GPIO3D6_JTAG_TMS,
GPIO3D6_HOST_DRV_VBUS,
GPIO3D5_SHIFT = 10,
GPIO3D5_MASK = 3,
GPIO3D5_GPIO = 0,
GPIO3D5_PWM_2,
GPIO3D5_JTAG_TCK,
GPIO3D5_OTG_DRV_VBUS,
GPIO3D4_SHIFT = 8,
GPIO3D4_MASK = 3,
GPIO3D4_GPIO = 0,
GPIO3D4_PWM_1,
GPIO3D4_JTAG_TRSTN,
GPIO3D3_SHIFT = 6,
GPIO3D3_MASK = 3,
GPIO3D3_GPIO = 0,
GPIO3D3_PWM_0,
GPIO3D2_SHIFT = 4,
GPIO3D2_MASK = 3,
GPIO3D2_GPIO = 0,
GPIO3D2_SDMMC1_INT_N,
GPIO3D1_SHIFT = 2,
GPIO3D1_MASK = 3,
GPIO3D1_GPIO = 0,
GPIO3D1_SDMMC1_BACKEND_PWR,
GPIO3D1_MII_MDCLK,
GPIO3D0_SHIFT = 0,
GPIO3D0_MASK = 3,
GPIO3D0_GPIO = 0,
GPIO3D0_SDMMC1_PWR_EN,
GPIO3D0_MII_MD,
};
/* GRF_SOC_CON0 */ /* GRF_SOC_CON0 */
enum { enum {
HSADC_CLK_DIR_SHIFT = 15, HSADC_CLK_DIR_SHIFT = 15,

380
drivers/pinctrl/rockchip/pinctrl_rk3188.c
View File

@ -20,6 +20,386 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* GRF_GPIO0D_IOMUX */
enum {
GPIO0D7_SHIFT = 14,
GPIO0D7_MASK = 1,
GPIO0D7_GPIO = 0,
GPIO0D7_SPI1_CSN0,
GPIO0D6_SHIFT = 12,
GPIO0D6_MASK = 1,
GPIO0D6_GPIO = 0,
GPIO0D6_SPI1_CLK,
GPIO0D5_SHIFT = 10,
GPIO0D5_MASK = 1,
GPIO0D5_GPIO = 0,
GPIO0D5_SPI1_TXD,
GPIO0D4_SHIFT = 8,
GPIO0D4_MASK = 1,
GPIO0D4_GPIO = 0,
GPIO0D4_SPI0_RXD,
GPIO0D3_SHIFT = 6,
GPIO0D3_MASK = 3,
GPIO0D3_GPIO = 0,
GPIO0D3_FLASH_CSN3,
GPIO0D3_EMMC_RSTN_OUT,
GPIO0D2_SHIFT = 4,
GPIO0D2_MASK = 3,
GPIO0D2_GPIO = 0,
GPIO0D2_FLASH_CSN2,
GPIO0D2_EMMC_CMD,
GPIO0D1_SHIFT = 2,
GPIO0D1_MASK = 1,
GPIO0D1_GPIO = 0,
GPIO0D1_FLASH_CSN1,
GPIO0D0_SHIFT = 0,
GPIO0D0_MASK = 3,
GPIO0D0_GPIO = 0,
GPIO0D0_FLASH_DQS,
GPIO0D0_EMMC_CLKOUT
};
/* GRF_GPIO1A_IOMUX */
enum {
GPIO1A7_SHIFT = 14,
GPIO1A7_MASK = 3,
GPIO1A7_GPIO = 0,
GPIO1A7_UART1_RTS_N,
GPIO1A7_SPI0_CSN0,
GPIO1A6_SHIFT = 12,
GPIO1A6_MASK = 3,
GPIO1A6_GPIO = 0,
GPIO1A6_UART1_CTS_N,
GPIO1A6_SPI0_CLK,
GPIO1A5_SHIFT = 10,
GPIO1A5_MASK = 3,
GPIO1A5_GPIO = 0,
GPIO1A5_UART1_SOUT,
GPIO1A5_SPI0_TXD,
GPIO1A4_SHIFT = 8,
GPIO1A4_MASK = 3,
GPIO1A4_GPIO = 0,
GPIO1A4_UART1_SIN,
GPIO1A4_SPI0_RXD,
GPIO1A3_SHIFT = 6,
GPIO1A3_MASK = 1,
GPIO1A3_GPIO = 0,
GPIO1A3_UART0_RTS_N,
GPIO1A2_SHIFT = 4,
GPIO1A2_MASK = 1,
GPIO1A2_GPIO = 0,
GPIO1A2_UART0_CTS_N,
GPIO1A1_SHIFT = 2,
GPIO1A1_MASK = 1,
GPIO1A1_GPIO = 0,
GPIO1A1_UART0_SOUT,
GPIO1A0_SHIFT = 0,
GPIO1A0_MASK = 1,
GPIO1A0_GPIO = 0,
GPIO1A0_UART0_SIN,
};
/* GRF_GPIO1B_IOMUX */
enum {
GPIO1B7_SHIFT = 14,
GPIO1B7_MASK = 1,
GPIO1B7_GPIO = 0,
GPIO1B7_SPI0_CSN1,
GPIO1B6_SHIFT = 12,
GPIO1B6_MASK = 3,
GPIO1B6_GPIO = 0,
GPIO1B6_SPDIF_TX,
GPIO1B6_SPI1_CSN1,
GPIO1B5_SHIFT = 10,
GPIO1B5_MASK = 3,
GPIO1B5_GPIO = 0,
GPIO1B5_UART3_RTS_N,
GPIO1B5_RESERVED,
GPIO1B4_SHIFT = 8,
GPIO1B4_MASK = 3,
GPIO1B4_GPIO = 0,
GPIO1B4_UART3_CTS_N,
GPIO1B4_GPS_RFCLK,
GPIO1B3_SHIFT = 6,
GPIO1B3_MASK = 3,
GPIO1B3_GPIO = 0,
GPIO1B3_UART3_SOUT,
GPIO1B3_GPS_SIG,
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3,
GPIO1B2_GPIO = 0,
GPIO1B2_UART3_SIN,
GPIO1B2_GPS_MAG,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3,
GPIO1B1_GPIO = 0,
GPIO1B1_UART2_SOUT,
GPIO1B1_JTAG_TDO,
GPIO1B0_SHIFT = 0,
GPIO1B0_MASK = 3,
GPIO1B0_GPIO = 0,
GPIO1B0_UART2_SIN,
GPIO1B0_JTAG_TDI,
};
/* GRF_GPIO1D_IOMUX */
enum {
GPIO1D7_SHIFT = 14,
GPIO1D7_MASK = 1,
GPIO1D7_GPIO = 0,
GPIO1D7_I2C4_SCL,
GPIO1D6_SHIFT = 12,
GPIO1D6_MASK = 1,
GPIO1D6_GPIO = 0,
GPIO1D6_I2C4_SDA,
GPIO1D5_SHIFT = 10,
GPIO1D5_MASK = 1,
GPIO1D5_GPIO = 0,
GPIO1D5_I2C2_SCL,
GPIO1D4_SHIFT = 8,
GPIO1D4_MASK = 1,
GPIO1D4_GPIO = 0,
GPIO1D4_I2C2_SDA,
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = 1,
GPIO1D3_GPIO = 0,
GPIO1D3_I2C1_SCL,
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = 1,
GPIO1D2_GPIO = 0,
GPIO1D2_I2C1_SDA,
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = 1,
GPIO1D1_GPIO = 0,
GPIO1D1_I2C0_SCL,
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = 1,
GPIO1D0_GPIO = 0,
GPIO1D0_I2C0_SDA,
};
/* GRF_GPIO3A_IOMUX */
enum {
GPIO3A7_SHIFT = 14,
GPIO3A7_MASK = 1,
GPIO3A7_GPIO = 0,
GPIO3A7_SDMMC0_DATA3,
GPIO3A6_SHIFT = 12,
GPIO3A6_MASK = 1,
GPIO3A6_GPIO = 0,
GPIO3A6_SDMMC0_DATA2,
GPIO3A5_SHIFT = 10,
GPIO3A5_MASK = 1,
GPIO3A5_GPIO = 0,
GPIO3A5_SDMMC0_DATA1,
GPIO3A4_SHIFT = 8,
GPIO3A4_MASK = 1,
GPIO3A4_GPIO = 0,
GPIO3A4_SDMMC0_DATA0,
GPIO3A3_SHIFT = 6,
GPIO3A3_MASK = 1,
GPIO3A3_GPIO = 0,
GPIO3A3_SDMMC0_CMD,
GPIO3A2_SHIFT = 4,
GPIO3A2_MASK = 1,
GPIO3A2_GPIO = 0,
GPIO3A2_SDMMC0_CLKOUT,
GPIO3A1_SHIFT = 2,
GPIO3A1_MASK = 1,
GPIO3A1_GPIO = 0,
GPIO3A1_SDMMC0_PWREN,
GPIO3A0_SHIFT = 0,
GPIO3A0_MASK = 1,
GPIO3A0_GPIO = 0,
GPIO3A0_SDMMC0_RSTN,
};
/* GRF_GPIO3B_IOMUX */
enum {
GPIO3B7_SHIFT = 14,
GPIO3B7_MASK = 3,
GPIO3B7_GPIO = 0,
GPIO3B7_CIF_DATA11,
GPIO3B7_I2C3_SCL,
GPIO3B6_SHIFT = 12,
GPIO3B6_MASK = 3,
GPIO3B6_GPIO = 0,
GPIO3B6_CIF_DATA10,
GPIO3B6_I2C3_SDA,
GPIO3B5_SHIFT = 10,
GPIO3B5_MASK = 3,
GPIO3B5_GPIO = 0,
GPIO3B5_CIF_DATA1,
GPIO3B5_HSADC_DATA9,
GPIO3B4_SHIFT = 8,
GPIO3B4_MASK = 3,
GPIO3B4_GPIO = 0,
GPIO3B4_CIF_DATA0,
GPIO3B4_HSADC_DATA8,
GPIO3B3_SHIFT = 6,
GPIO3B3_MASK = 1,
GPIO3B3_GPIO = 0,
GPIO3B3_CIF_CLKOUT,
GPIO3B2_SHIFT = 4,
GPIO3B2_MASK = 1,
GPIO3B2_GPIO = 0,
/* no muxes */
GPIO3B1_SHIFT = 2,
GPIO3B1_MASK = 1,
GPIO3B1_GPIO = 0,
GPIO3B1_SDMMC0_WRITE_PRT,
GPIO3B0_SHIFT = 0,
GPIO3B0_MASK = 1,
GPIO3B0_GPIO = 0,
GPIO3B0_SDMMC_DETECT_N,
};
/* GRF_GPIO3C_IOMUX */
enum {
GPIO3C7_SHIFT = 14,
GPIO3C7_MASK = 3,
GPIO3C7_GPIO = 0,
GPIO3C7_SDMMC1_WRITE_PRT,
GPIO3C7_RMII_CRS_DVALID,
GPIO3C7_RESERVED,
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = 3,
GPIO3C6_GPIO = 0,
GPIO3C6_SDMMC1_DECTN,
GPIO3C6_RMII_RX_ERR,
GPIO3C6_RESERVED,
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = 3,
GPIO3C5_GPIO = 0,
GPIO3C5_SDMMC1_CLKOUT,
GPIO3C5_RMII_CLKOUT,
GPIO3C5_RMII_CLKIN,
GPIO3C4_SHIFT = 8,
GPIO3C4_MASK = 3,
GPIO3C4_GPIO = 0,
GPIO3C4_SDMMC1_DATA3,
GPIO3C4_RMII_RXD1,
GPIO3C4_RESERVED,
GPIO3C3_SHIFT = 6,
GPIO3C3_MASK = 3,
GPIO3C3_GPIO = 0,
GPIO3C3_SDMMC1_DATA2,
GPIO3C3_RMII_RXD0,
GPIO3C3_RESERVED,
GPIO3C2_SHIFT = 4,
GPIO3C2_MASK = 3,
GPIO3C2_GPIO = 0,
GPIO3C2_SDMMC1_DATA1,
GPIO3C2_RMII_TXD0,
GPIO3C2_RESERVED,
GPIO3C1_SHIFT = 2,
GPIO3C1_MASK = 3,
GPIO3C1_GPIO = 0,
GPIO3C1_SDMMC1_DATA0,
GPIO3C1_RMII_TXD1,
GPIO3C1_RESERVED,
GPIO3C0_SHIFT = 0,
GPIO3C0_MASK = 3,
GPIO3C0_GPIO = 0,
GPIO3C0_SDMMC1_CMD,
GPIO3C0_RMII_TX_EN,
GPIO3C0_RESERVED,
};
/* GRF_GPIO3D_IOMUX */
enum {
GPIO3D6_SHIFT = 12,
GPIO3D6_MASK = 3,
GPIO3D6_GPIO = 0,
GPIO3D6_PWM_3,
GPIO3D6_JTAG_TMS,
GPIO3D6_HOST_DRV_VBUS,
GPIO3D5_SHIFT = 10,
GPIO3D5_MASK = 3,
GPIO3D5_GPIO = 0,
GPIO3D5_PWM_2,
GPIO3D5_JTAG_TCK,
GPIO3D5_OTG_DRV_VBUS,
GPIO3D4_SHIFT = 8,
GPIO3D4_MASK = 3,
GPIO3D4_GPIO = 0,
GPIO3D4_PWM_1,
GPIO3D4_JTAG_TRSTN,
GPIO3D3_SHIFT = 6,
GPIO3D3_MASK = 3,
GPIO3D3_GPIO = 0,
GPIO3D3_PWM_0,
GPIO3D2_SHIFT = 4,
GPIO3D2_MASK = 3,
GPIO3D2_GPIO = 0,
GPIO3D2_SDMMC1_INT_N,
GPIO3D1_SHIFT = 2,
GPIO3D1_MASK = 3,
GPIO3D1_GPIO = 0,
GPIO3D1_SDMMC1_BACKEND_PWR,
GPIO3D1_MII_MDCLK,
GPIO3D0_SHIFT = 0,
GPIO3D0_MASK = 3,
GPIO3D0_GPIO = 0,
GPIO3D0_SDMMC1_PWR_EN,
GPIO3D0_MII_MD,
};
struct rk3188_pinctrl_priv { struct rk3188_pinctrl_priv {
struct rk3188_grf *grf; struct rk3188_grf *grf;
struct rk3188_pmu *pmu; struct rk3188_pmu *pmu;