misc: Add gdsys_ioep driver
Add driver for the IHS IO endpoint on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
parent
004e67c216
commit
7e86242b2b
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@ -0,0 +1,20 @@
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gdsys IO endpoint of IHS FPGA devices
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The IO endpoint of IHS FPGA devices is a packet-based transmission interface
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that allows interconnected gdsys devices to send and receive data over the
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FPGA's main ethernet connection.
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Required properties:
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- compatible: must be "gdsys,io-endpoint"
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- reg: describes the address and length of the endpoint's register map (within
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the FPGA's register space)
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Example:
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fpga0_ep0 {
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compatible = "gdsys,io-endpoint";
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reg = <0x020 0x10
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0x320 0x10
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0x340 0x10
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0x360 0x10>;
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};
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@ -277,4 +277,10 @@ config GDSYS_RXAUI_CTRL
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depends on MISC
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depends on MISC
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help
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help
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Support gdsys FPGA's RXAUI control.
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Support gdsys FPGA's RXAUI control.
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config GDSYS_IOEP
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bool "Enable gdsys IOEP driver"
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depends on MISC
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help
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Support gdsys FPGA's IO endpoint driver.
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endmenu
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endmenu
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@ -53,4 +53,5 @@ obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
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obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
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obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
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obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
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obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
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obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
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obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
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obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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@ -0,0 +1,209 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* based on the cmd_ioloop driver/command, which is
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*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <misc.h>
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#include <regmap.h>
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#include "gdsys_ioep.h"
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/**
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* struct gdsys_ioep_priv - Private data structure for IOEP devices
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* @map: Register map to be used for the device
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* @state: Flag to keep the current status of the RX control (enabled/disabled)
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*/
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struct gdsys_ioep_priv {
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struct regmap *map;
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bool state;
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};
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/**
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* enum last_spec - Convenience enum for read data sanity check
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* @READ_DATA_IS_LAST: The data to be read should be the final data of the
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* current packet
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* @READ_DATA_IS_NOT_LAST: The data to be read should not be the final data of
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* the current packet
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*/
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enum last_spec {
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READ_DATA_IS_LAST,
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READ_DATA_IS_NOT_LAST,
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};
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static int gdsys_ioep_set_receive(struct udevice *dev, bool val)
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{
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struct gdsys_ioep_priv *priv = dev_get_priv(dev);
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u16 state;
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priv->state = !priv->state;
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if (val)
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state = CTRL_PROC_RECEIVE_ENABLE;
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else
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state = ~CTRL_PROC_RECEIVE_ENABLE;
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gdsys_ioep_set(priv->map, tx_control, state);
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if (val) {
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/* Set device address to dummy 1 */
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gdsys_ioep_set(priv->map, device_address, 1);
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}
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return !priv->state;
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}
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static int gdsys_ioep_send(struct udevice *dev, int offset,
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const void *buf, int size)
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{
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struct gdsys_ioep_priv *priv = dev_get_priv(dev);
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int k;
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u16 *p = (u16 *)buf;
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for (k = 0; k < size; ++k)
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gdsys_ioep_set(priv->map, transmit_data, *(p++));
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gdsys_ioep_set(priv->map, tx_control, CTRL_PROC_RECEIVE_ENABLE |
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CTRL_FLUSH_TRANSMIT_BUFFER);
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return 0;
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}
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/**
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* receive_byte_buffer() - Read data from a IOEP device
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* @dev: The IOEP device to read data from
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* @len: The length of the data to read
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* @buffer: The buffer to read the data into
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* @last_spec: Flag to indicate if the data to be read in this call should be
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* the final data of the current packet (i.e. it should be empty
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* after this read)
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*
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* Return: 0 if OK, -ve on error
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*/
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static int receive_byte_buffer(struct udevice *dev, uint len,
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u16 *buffer, enum last_spec last_spec)
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{
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struct gdsys_ioep_priv *priv = dev_get_priv(dev);
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int k;
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int ret = -EIO;
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for (k = 0; k < len; ++k) {
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u16 rx_tx_status;
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gdsys_ioep_get(priv->map, receive_data, buffer++);
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gdsys_ioep_get(priv->map, rx_tx_status, &rx_tx_status);
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/*
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* Sanity check: If the data read should have been the last,
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* but wasn't, something is wrong
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*/
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if (k == (len - 1) && (last_spec == READ_DATA_IS_NOT_LAST ||
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rx_tx_status & STATE_RX_DATA_LAST))
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ret = 0;
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}
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if (ret)
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debug("%s: Error while receiving bufer (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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static int gdsys_ioep_receive(struct udevice *dev, int offset, void *buf,
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int size)
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{
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int ret;
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struct io_generic_packet header;
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u16 *p = (u16 *)buf;
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const int header_words = sizeof(struct io_generic_packet) / sizeof(u16);
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uint len;
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/* Read the packet header */
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ret = receive_byte_buffer(dev, header_words, p, READ_DATA_IS_NOT_LAST);
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if (ret) {
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debug("%s: Failed to read header data (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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memcpy(&header, p, header_words * sizeof(u16));
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p += header_words;
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/* Get payload data length */
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len = (header.packet_length + 1) / sizeof(u16);
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/* Read the packet payload */
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ret = receive_byte_buffer(dev, len, p, READ_DATA_IS_LAST);
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if (ret) {
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debug("%s: Failed to read payload data (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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return 0;
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}
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static int gdsys_ioep_get_and_reset_status(struct udevice *dev, int msgid,
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void *tx_msg, int tx_size,
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void *rx_msg, int rx_size)
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{
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struct gdsys_ioep_priv *priv = dev_get_priv(dev);
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const u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
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STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
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STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
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u16 *status = rx_msg;
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gdsys_ioep_get(priv->map, rx_tx_status, status);
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gdsys_ioep_set(priv->map, rx_tx_status, *status);
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return (*status & mask) ? 1 : 0;
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}
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static const struct misc_ops gdsys_ioep_ops = {
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.set_enabled = gdsys_ioep_set_receive,
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.write = gdsys_ioep_send,
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.read = gdsys_ioep_receive,
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.call = gdsys_ioep_get_and_reset_status,
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};
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static int gdsys_ioep_probe(struct udevice *dev)
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{
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struct gdsys_ioep_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
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if (ret) {
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debug("%s: Could not initialize regmap (err = %d)",
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dev->name, ret);
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return ret;
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}
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priv->state = false;
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return 0;
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}
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static const struct udevice_id gdsys_ioep_ids[] = {
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{ .compatible = "gdsys,io-endpoint" },
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{ }
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};
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U_BOOT_DRIVER(gdsys_ioep) = {
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.name = "gdsys_ioep",
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.id = UCLASS_MISC,
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.ops = &gdsys_ioep_ops,
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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.of_match = gdsys_ioep_ids,
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.probe = gdsys_ioep_probe,
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.priv_auto_alloc_size = sizeof(struct gdsys_ioep_priv),
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};
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@ -0,0 +1,137 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#ifndef __GDSYS_IOEP_H_
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#define __GDSYS_IOEP_H_
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/**
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* struct io_generic_packet - header structure for GDSYS IOEP packets
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* @target_address: Target protocol address of the packet.
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* @source_address: Source protocol address of the packet.
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* @packet_type: Packet type.
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* @bc: Block counter (filled in by FPGA).
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* @packet_length: Length of the packet's payload bytes.
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*/
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struct io_generic_packet {
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u16 target_address;
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u16 source_address;
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u8 packet_type;
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u8 bc;
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u16 packet_length;
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} __attribute__((__packed__));
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/**
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* struct gdsys_ioep_regs - Registers of a IOEP device
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* @transmit_data: Register that receives data to be sent
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* @tx_control: TX control register
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* @receive_data: Register filled with the received data
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* @rx_tx_status: RX/TX status register
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* @device_address: Register for setting/reading the device's address
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* @target_address: Register for setting/reading the remote endpoint's address
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* @int_enable: Interrupt/Interrupt enable register
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*/
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struct gdsys_ioep_regs {
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u16 transmit_data;
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u16 tx_control;
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u16 receive_data;
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u16 rx_tx_status;
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u16 device_address;
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u16 target_address;
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u16 int_enable;
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};
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/**
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* gdsys_ioep_set() - Convenience macro to write registers of a IOEP device
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* @map: Register map to write the value in
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* @member: Name of the member in the gdsys_ioep_regs structure to write
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* @val: Value to write to the register
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*/
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#define gdsys_ioep_set(map, member, val) \
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regmap_set(map, struct gdsys_ioep_regs, member, val)
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/**
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* gdsys_ioep_get() - Convenience macro to read registers of a IOEP device
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* @map: Register map to read the value from
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* @member: Name of the member in the gdsys_ioep_regs structure to read
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* @valp: Pointer to buffer to read the register value into
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*/
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#define gdsys_ioep_get(map, member, valp) \
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regmap_get(map, struct gdsys_ioep_regs, member, valp)
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/**
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* enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status
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* register
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* @STATE_TX_PACKET_BUILDING: The device is currently building a packet
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* (and accepting data for it)
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* @STATE_TX_TRANSMITTING: A packet is currenly being transmitted
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* @STATE_TX_BUFFER_FULL: The TX buffer is full
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* @STATE_TX_ERR: A TX error occurred
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* @STATE_RECEIVE_TIMEOUT: A receive timeout occurred
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* @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet
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* occurred
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* @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet
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* occurred
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* @STATE_RX_DIST_ERR: A error occurred in the distribution block
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* @STATE_RX_LENGTH_ERR: A length invalid error occurred
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* @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two
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* non-increasing frame count numbers
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* encountered)
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* @STATE_RX_FCS_ERR: A CRC error occurred
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* @STATE_RX_PACKET_DROPPED: A RX packet has been dropped
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* @STATE_RX_DATA_LAST: The data to be read is the final data of the
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* current packet
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* @STATE_RX_DATA_FIRST: The data to be read is the first data of the
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* current packet
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* @STATE_RX_DATA_AVAILABLE: RX data is available to be read
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*/
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enum rx_tx_status_values {
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STATE_TX_PACKET_BUILDING = BIT(0),
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STATE_TX_TRANSMITTING = BIT(1),
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STATE_TX_BUFFER_FULL = BIT(2),
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STATE_TX_ERR = BIT(3),
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STATE_RECEIVE_TIMEOUT = BIT(4),
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STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
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STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
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STATE_RX_DIST_ERR = BIT(7),
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STATE_RX_LENGTH_ERR = BIT(8),
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STATE_RX_FRAME_CTR_ERR = BIT(9),
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STATE_RX_FCS_ERR = BIT(10),
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STATE_RX_PACKET_DROPPED = BIT(11),
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STATE_RX_DATA_LAST = BIT(12),
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STATE_RX_DATA_FIRST = BIT(13),
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STATE_RX_DATA_AVAILABLE = BIT(15),
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};
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/**
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* enum tx_control_values - Enum to describe the fields of the tx_control
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* register
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* @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor
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* @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data)
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*/
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enum tx_control_values {
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CTRL_PROC_RECEIVE_ENABLE = BIT(12),
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CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum int_enable_values - Enum to describe the fields of the int_enable
|
||||||
|
* register
|
||||||
|
* @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet
|
||||||
|
* data can be transmitted to the
|
||||||
|
* device)
|
||||||
|
* @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted
|
||||||
|
* @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received
|
||||||
|
* @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be
|
||||||
|
* read
|
||||||
|
*/
|
||||||
|
enum int_enable_values {
|
||||||
|
IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
|
||||||
|
IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
|
||||||
|
IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
|
||||||
|
IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __GDSYS_IOEP_H_ */
|
||||||
Loading…
Reference in New Issue