From a9bdd67653c026d3f568375ca8e48fb5014c62c9 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Fri, 16 Feb 2018 16:07:24 +0100 Subject: [PATCH 1/5] rockchip: clk: rk3399: handle clk_enable requests for GMAC Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3399 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the enable-op of the rk3399 clk driver to signal success to the caller when the clocks for the GMAC are enabled. References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich Tested-by: Klaus Goger --- drivers/clk/rockchip/clk_rk3399.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 42926ba323..8822d3a9a8 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -997,6 +997,16 @@ static int rk3399_clk_enable(struct clk *clk) case HCLK_HOST1: case HCLK_HOST1_ARB: return 0; + + case SCLK_MAC: + case SCLK_MAC_RX: + case SCLK_MAC_TX: + case SCLK_MACREF: + case SCLK_MACREF_OUT: + case ACLK_GMAC: + case PCLK_GMAC: + /* Required to successfully probe the Designware GMAC driver */ + return 0; } debug("%s: unsupported clk %ld\n", __func__, clk->id); From 35a69a3b01298e605025f4758d79f667463c9ee1 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Fri, 16 Feb 2018 16:07:25 +0100 Subject: [PATCH 2/5] rockchip: clk: rk3368: handle clk_enable requests for GMAC Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3368 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the RK3368 clk driver to: (a) provide a enable op (b) signals success to the caller when the clocks for the GMAC are enabled (no actual action is necessary as the gates are open after reset) References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich Tested-by: Klaus Goger --- drivers/clk/rockchip/clk_rk3368.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3ac9add527..ea00f1fc9c 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -568,12 +568,31 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par return -ENOENT; } +static int rk3368_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case SCLK_MAC: + case SCLK_MAC_RX: + case SCLK_MAC_TX: + case SCLK_MACREF: + case SCLK_MACREF_OUT: + case ACLK_GMAC: + case PCLK_GMAC: + /* Required to successfully probe the Designware GMAC driver */ + return 0; + } + + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; +} + static struct clk_ops rk3368_clk_ops = { .get_rate = rk3368_clk_get_rate, .set_rate = rk3368_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3368_clk_set_parent, #endif + .enable = rk3368_clk_enable, }; static int rk3368_clk_probe(struct udevice *dev) From 849f672bdbdb8ef9ae92063e14d164db32a3c341 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Feb 2018 13:13:10 +0530 Subject: [PATCH 3/5] rockchip: rk3288: Add TPL_LDSCRIPT Due to size limitations in SPL by adding falcon mode, rk3288 support TPL. In order to not overlap SPL_TEXT_BASE add TPL_TEXT_BASE with u-boot-tpl.lds that intern call u-boot-spl.lds with proper TEXT_BASE values. Signed-off-by: Jagan Teki Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Kconfig | 7 +++++++ arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds | 10 ++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1e5a7bb79b..d9218da64f 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -72,6 +72,13 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +if ROCKCHIP_RK3288 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds" + +endif + config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 diff --git a/arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds new file mode 100644 index 0000000000..c7a60929e6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#include "../../cpu/u-boot-spl.lds" From 33554fcec99b7c8b57e004fdf18588ce21d85e68 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Feb 2018 13:13:11 +0530 Subject: [PATCH 4/5] rockchip: rk3288: Fix wrong TPL_TEXT_BASE TPL offset 0xff704004 is unaligned address which is adding nearest 8-bytes for next instruction, So 0xff704004 is adding 0x20 for proper alignment which is causing the next instruction data 0xefffffff is moved. Hexdump with overlaped bytes: ----------------------------- 0000000 0000 0000 0000 0000 0000 0000 0000 0000 0000010 0000 0000 0000 0000 0000 0000 ffff eaff So, Fix the TEXT_BASE for proper aligned address 0xff704000 Signed-off-by: Jagan Teki Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/Kconfig | 3 +++ configs/vyasa-rk3288_defconfig | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d9218da64f..0adaed4367 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -77,6 +77,9 @@ if ROCKCHIP_RK3288 config TPL_LDSCRIPT default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds" +config TPL_TEXT_BASE + default 0xff704000 + endif config ROCKCHIP_RK3328 diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 1a8a9a8c60..4c760414d3 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_TPL_TEXT_BASE=0xff704004 CONFIG_TARGET_VYASA_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa" From 434d5a00a4578f826e7e2cef29bf2388dd760a88 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Fri, 23 Feb 2018 17:36:41 +0100 Subject: [PATCH 5/5] rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL The device-tree node for the PMU clk controller assigns to its parent (i.e. PLL_PPLL) even though this clock currently is set up statically by an init-function. In order to avoid unexpected failures, a simple implementation of set_rate (which accepts requests, but notifies the caller of the preset frequency in its return value) and get_rate (which always returns the preset frequency) are added. Note that this is required for the RK808 PMIC to probe successfully on the RK3399-Q7, following the support for the assigned-clocks property. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Philipp Tomsich Tested-by: Klaus Goger --- drivers/clk/rockchip/clk_rk3399.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 8822d3a9a8..fb74c441ff 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1246,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) ulong rate = 0; switch (clk->id) { + case PLL_PPLL: + return PPLL_HZ; case PCLK_RKPWM_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; @@ -1267,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) ulong ret = 0; switch (clk->id) { + case PLL_PPLL: + /* + * This has already been set up and we don't want/need + * to change it here. Accept the request though, as the + * device-tree has this in an 'assigned-clocks' list. + */ + return PPLL_HZ; case SCLK_I2C0_PMU: case SCLK_I2C4_PMU: case SCLK_I2C8_PMU: