diff --git a/board/nm/nmhw21/board.c b/board/nm/nmhw21/board.c
index 1166c6033a..f2c28779d9 100644
--- a/board/nm/nmhw21/board.c
+++ b/board/nm/nmhw21/board.c
@@ -382,6 +382,27 @@ static void pmic_fix_config(void)
 	}
 }
 
+static void pmic_disable_auto_mode(void)
+{
+	/*
+	 * In some rare cases the automatic mode switching between synchronous and sleep
+	 * mode can lead to PMIC issues. In this case the rail output is disabled.
+	 * The following code fixes the operation mode to synchronous operation.
+	 */
+	uint8_t val = 0;
+
+	/* Check whether config has automatic mode defined */
+	(void)da9063_get_reg(PMIC_REG_BCORE1_CONF, &val);
+	if ((val & PMIC_CONF_MODE_MASK) == PMIC_CONF_MODE_AUTO)
+	{
+		(void)da9063_set_reg(PMIC_REG_BCORE1_CONF, PMIC_CONF_MODE_SYNC | 0x01);
+		(void)da9063_set_reg(PMIC_REG_BCORE2_CONF, PMIC_CONF_MODE_SYNC | 0x01);
+		(void)da9063_set_reg(PMIC_REG_BPERI_CONF, PMIC_CONF_MODE_SYNC | 0x01);
+		(void)da9063_set_reg(PMIC_REG_BIO_CONF, PMIC_CONF_MODE_SYNC | 0x01);
+		(void)da9063_set_reg(PMIC_REG_BMEM_CONF, PMIC_CONF_MODE_SYNC | 0x01);
+	}
+}
+
 static void pmic_ignition_gate_on(void)
 {
 	uint8_t val;
@@ -415,6 +436,9 @@ static void init_pmic_spl(void)
 	/* Fix old configs (mainly prototype boards) */
 	pmic_fix_config();
 
+	/* Disable automatic mode switching */
+	pmic_disable_auto_mode();
+
 	/* Enable +3V3_GNSS (LDO6) */
 	(void)da9063_set_reg(PMIC_REG_LDO6_CONT, PMIC_LDOx_EN_MASK);
 	mdelay(2);
diff --git a/board/nm/nmhw21/da9063.h b/board/nm/nmhw21/da9063.h
index b1fc76beb2..3b2cfab2d6 100644
--- a/board/nm/nmhw21/da9063.h
+++ b/board/nm/nmhw21/da9063.h
@@ -41,6 +41,18 @@
 #define PMIC_REG_BUCK_ILIM_B	0x9B
 #define PMIC_REG_BUCK_ILIM_C	0x9C
 
+#define PMIC_REG_BCORE1_CONF	0x9E	/* Configuration register of BCORE1 */
+#define PMIC_REG_BCORE2_CONF	0x9D	/* Configuration register of BCORE2 */
+#define PMIC_REG_BPERI_CONF	0xA2	/* Configuration register of BPERI */
+#define PMIC_REG_BIO_CONF	0xA0	/* Configuration register of BIO */
+#define PMIC_REG_BMEM_CONF	0xA1	/* Configuration register of BMEM */
+
+#define PMIC_CONF_MODE_MASK	0xC0
+#define PMIC_CONF_MODE_SLEEP	0x40
+#define PMIC_CONF_MODE_SYNC	0x80
+#define PMIC_CONF_MODE_AUTO	0xC0
+
+
 #define PMIC_REG_BBAT_CONT	0xC5	/* Control register for backup battery */
 
 #define PMIC_REG_CONFIG_E	0x10A