From 89d2afec023b87100c7a230c988892326dcaaf5e Mon Sep 17 00:00:00 2001 From: Rene Straub Date: Thu, 4 Jan 2018 17:35:05 +0100 Subject: [PATCH] nrhw20: prepare migration from hw16 gpio settings --- board/nm/nrhw20/mux.c | 246 ++++++++++++++++++++++++++++++++- board/nm/nrhw20/shield_can.c | 30 ++-- board/nm/nrhw20/shield_comio.c | 35 ++--- 3 files changed, 276 insertions(+), 35 deletions(-) diff --git a/board/nm/nrhw20/mux.c b/board/nm/nrhw20/mux.c index 749ab79180..94bb0a7cc2 100644 --- a/board/nm/nrhw20/mux.c +++ b/board/nm/nrhw20/mux.c @@ -1,6 +1,7 @@ /* * mux.c * + * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or @@ -18,9 +19,12 @@ #include #include #include -#include #include "board.h" + +#ifdef NRHW20_ON_HW16_MODE + +#if 0 /* TODO: Remove */ static struct module_pin_mux uart2_pin_mux[] = { {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ @@ -44,6 +48,7 @@ static struct module_pin_mux uart5_pin_mux[] = { {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ {-1}, }; +#endif static struct module_pin_mux i2c0_pin_mux[] = { {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | @@ -170,6 +175,7 @@ void enable_uart1_pin_mux(void) configure_module_pin_mux(uart1_netbird_pin_mux); } +/* void enable_uart2_pin_mux(void) { configure_module_pin_mux(uart2_pin_mux); @@ -194,12 +200,14 @@ void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } +*/ /* * The AM335x GP EVM, if daughter card(s) are connected, can have 8 * different profiles. These profiles determine what peripherals are * valid and need pinmux to be configured. */ +/* #define PROFILE_NONE 0x0 #define PROFILE_0 (1 << 0) #define PROFILE_1 (1 << 1) @@ -211,10 +219,10 @@ void enable_i2c0_pin_mux(void) #define PROFILE_7 (1 << 7) #define PROFILE_MASK 0x7 #define PROFILE_ALL 0xFF - +*/ /* CPLD registers */ -#define I2C_CPLD_ADDR 0x35 -#define CFG_REG 0x10 +/*#define I2C_CPLD_ADDR 0x35*/ +/*#define CFG_REG 0x10*/ void enable_board_pin_mux(void) { @@ -227,3 +235,233 @@ void enable_board_pin_mux(void) configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(unused_netbird_pin_mux); } + + +#else /* NRHW 20 Board */ + +static struct module_pin_mux gpio_pin_mux[] = { + /* + * GPIO0_2: RST_GNSS~ + * GPIO0_3: GEOFENCE_GNSS + * GPIO0_4: RTK_STAT_GNSS + * GPIO0_5: EXTINT_GNSS + * GPIO0_6: TIMEPULSE_GNSS + * GPIO0_7: PWM + * GPIO0_16: RST_PHY~ + * GPIO0_17: PMIC FAULT + * GPIO0_27: RST_SHIELD~ + * GPIO0_31: GSM_WAKE + * + * GPIO1_14: DIG_OUT + * GPIO1_15: DIG_IN + * GPIO1_20: BT_EN + * GPIO1_21: GSM_PWR_EN + * GPIO1_25: RST_GSM + * GPIO1_26: WLAN_EN + * GPIO1_27: WLAN_IRQ + * + * GPIO3_0: BUTTON + * GPIO3_4: PCIe_IO.WAKE + * GPIO3_9: PCIe_IO.W_DIS + * GPIO3_10: PCIe_IO.RST + * GPIO3_17: SIM_SEL + * GPIO3_21: RST_HUB~ (USB) + */ + + /* Bank 0 */ + /* GNSS Pins */ + {OFFSET(spi0_sclk), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (A17) gpio0[2] */ /* RST_GNSS */ + {OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (B17) gpio0[3] */ /* GEOFENCE_GNSS */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (B16) gpio0[4] */ /* RTK_STAT_GNSS */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (A16) gpio0[5] */ /* EXTINT_GNSS */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (C15) gpio0[6] */ /* TIMEPULSE_GNSS */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (C18) gpio0[7] */ /* IO_SHIELD */ + {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gpio0[16] */ /* RST_PHY~ */ + {OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS)}, /* (K15) gpio0[17] */ /* PMIC_FAULT */ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* (U12) gpio0[27] */ /* RST_SHIELD~ */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (U17) gpio0[31] */ /* GSM_WAKE */ /* TODO: INPUT, RXACTIVE? */ + /* TODO: Check gpmc_wpn */ + + /* Bank 1 */ + {OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)}, /* (V13) gpio1[14] */ /* DIG_OUT */ + {OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)}, /* (U13) gpio1[15] */ /* DIG_IN */ + {OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)}, /* (R14) gpio1[20] */ /* BT_EN */ + {OFFSET(gpmc_a5), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (V15) gpio1[21] */ /* GSM_PWR_EN */ + {OFFSET(gpmc_a9), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (U16) gpio1[25] */ /* RST_GSM */ + {OFFSET(gpmc_a10), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (T16) gpio1[26] */ /* WLAN_EN */ + {OFFSET(gpmc_a11), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (V17) gpio1[27] */ /* WLAN_IRQ */ /*TODO: RXACTIVE? */ + + /* TODO: What about all the unused GPMC pins ? */ + + + /* Bank 2 */ +#if 0 + /* TODO: What is this meant for? */ + {OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (R4) gpio2[9] */ /* SYSBOOT_3 */ + {OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (T1) gpio2[10] */ /* SYSBOOT_4 */ + + /* TODO: Check other unued pins from sysboot block */ + /* Ensure PU/PD does not work against external signal */ + /* + * SYSBOOT 0,1,5,12,13 = Low + * SYSBOOT 2 = High + */ +#endif + + /* Bank 3 */ + {OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (H16) gpio3[0] */ /* BUTTON */ + {OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)}, /* (J17) gpio3[4] */ /* PCIe_IO.WAKE */ + {OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)}, /* (K18) gpio3[9] */ /* PCIe_IO.W_DIS */ + {OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)}, /* (L18) gpio3[10] */ /* PCIe_IO.RST */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (C12) gpio3[17] */ /* SIM_SEL */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (A14) gpio3[21] */ /* RST_HUB~ */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (C17) I2C0_SDA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (C16) I2C0_SCL */ + {-1}, +}; + +static struct module_pin_mux i2c2_pin_mux[] = { + {OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (D17) I2C2_SCL */ + {OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (D18) I2C2_SDA */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + /* RMII */ + {OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE}, /* (H17) rmii1_crs */ + /* TODO: Check whether pin can be disabled, resistor R1013 removed */ + {OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE}, /* (J15) rmii1_rxerr */ + {OFFSET(mii1_txen), MODE(1) | PULLUDDIS }, /* (J16) rmii1_txen */ + {OFFSET(mii1_txd0), MODE(1) | PULLUDDIS }, /* (K17) rmii1_txd0 */ + {OFFSET(mii1_txd1), MODE(1) | PULLUDDIS }, /* (K16) rmii1_txd1 */ + {OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE }, /* (M16) rmii1_rxd0 */ + {OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE }, /* (L15) rmii1_rxd1 */ + {OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE}, /* (H18) rmii1_refclk */ + + /* SMI */ + {OFFSET(mdio_clk), MODE(0) | PULLUDDIS }, /* (M18) mdio_clk */ + {OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE },/* (M17) mdio_data */ + + /* 25MHz Clock Output */ + {OFFSET(xdma_event_intr0), MODE(3) }, /* (A15) clkout1 (25 MHz clk for Switch) */ + {-1}, +}; + +static struct module_pin_mux mmc0_sdio_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux mmc1_emmc_pin_mux[] = { + {OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */ + {OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT0 */ + {OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */ + {-1}, +}; + +/* TODO: Check, configure as GPIO, instead of USB_DRVBUS */ +static struct module_pin_mux usb_pin_mux[] = { + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)}, /* (F16) USB0_DRVVBUS */ + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)}, /* (F15) USB1_DRVVBUS */ + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E15) UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (E16) UART0_TXD */ + /* TODO: Place same defaults for uart0_rts, uart_cts? */ + {-1}, +}; + +static struct module_pin_mux uart0_disabled_pin_mux[] = { + /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ + /* Mode 7 = GPIO */ + {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E15) GPIO1_10 */ + {OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E16) GPIO1_11 */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE )}, /* (E18) GPIO1_8 */ + {OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN )}, /* (E17) GPIO1_9 */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D16) uart1_rxd */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (D15) uart1_txd */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(mii1_rxd2), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* (L16) UART3_TXD */ + {OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN)}, /* (L17) UART3_RXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* (U2) UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* (U1) UART5_TXD */ + {OFFSET(lcd_data14), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* (V4) uart5_ctsn */ + {OFFSET(lcd_data15), (MODE(6) | PULLUDEN)}, /* (T5) uart5_rtsn */ + {-1}, +}; + +static struct module_pin_mux unused_pin_mux[] = { + {OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* SYSBOOT6 is not used pulldown active, receiver disabled */ + {OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* SYSBOOT7 is not used pulldown active, receiver disabled */ + {OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* SYSBOOT10 is not used pulldown active, receiver disabled */ + {OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* SYSBOOT11 is not used pulldown active, receiver disabled */ + + /* TODO: GPMCA1..3, A6..8 */ + + {-1}, +}; + + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(gpio_pin_mux); + + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_sdio_pin_mux); + configure_module_pin_mux(mmc1_emmc_pin_mux); + configure_module_pin_mux(usb_pin_mux); + + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(i2c2_pin_mux); + + configure_module_pin_mux(uart3_pin_mux); + configure_module_pin_mux(uart5_pin_mux); + + configure_module_pin_mux(unused_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void disable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_disabled_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +#endif diff --git a/board/nm/nrhw20/shield_can.c b/board/nm/nrhw20/shield_can.c index 99632eee56..36fa0a66a7 100644 --- a/board/nm/nrhw20/shield_can.c +++ b/board/nm/nrhw20/shield_can.c @@ -7,10 +7,12 @@ #include "shield.h" #include "board.h" -#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27) -#define NETBIRD_GPIO_LATCH GPIO_TO_PIN(0, 7) -#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 8) -#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10) +#define CAN_PORTS 2 + +#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27) +#define NETBIRD_GPIO_LATCH GPIO_TO_PIN(0, 7) +#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 8) +#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10) static int shield_slot_initialized = 0; @@ -18,21 +20,21 @@ static int shield_slot_initialized = 0; static struct module_pin_mux can_shield_netbird_pin_mux_config[] = { /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ - {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* CAN1 tx */ - {OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* CAN0 tx */ - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* Latch EN */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (E18) gpio1_8 */ /* Mode 0 */ + {OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (E15) gpio1_10 */ /* Mode 1 */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* Latch EN */ {-1}, }; static struct module_pin_mux can_shield_netbird_pin_mux_final[] = { - /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ - {OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)}, /* CAN1 tx */ - {OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* CAN1 rx */ - {OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* CAN0 rx */ - {OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)}, /* CAN0 tx */ + {OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* (E16) dcan0_rx */ + {OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)}, /* (E15) dcan0_tx */ + {OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* (E17) dcan1_rx */ + {OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)}, /* (E18) dcan1_tx */ {-1}, }; + static int request_gpios(void) { int ret; @@ -150,7 +152,6 @@ static int get_termination(const char* termination) static int get_mode_from_args(char * const argv[], int argc) { -#define CAN_PORTS 2 int terminations[CAN_PORTS]; int i; @@ -169,6 +170,7 @@ static int get_mode_from_args(char * const argv[], int argc) } /* Termination is inverse */ + /* TODO: Double check */ return (!terminations[0] << 0) | (!terminations[1] << 1); } @@ -182,6 +184,7 @@ static int set_shieldmode(char * const argv[], int argc) return configure_shieldmode(get_mode_from_args(argv, argc)); } +/* TODO: Static ? */ struct shield_t can_shield = { "dualcan", set_shieldmode }; @@ -190,4 +193,3 @@ void can_shield_init(void) { shield_register(&can_shield); } - diff --git a/board/nm/nrhw20/shield_comio.c b/board/nm/nrhw20/shield_comio.c index 2efac38db2..f43e992349 100644 --- a/board/nm/nrhw20/shield_comio.c +++ b/board/nm/nrhw20/shield_comio.c @@ -7,30 +7,31 @@ #include "shield.h" #include "board.h" -#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27) -#define NETBIRD_GPIO_LOAD GPIO_TO_PIN(1, 9) -#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 11) -#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10) - +/* TODO: Double Check */ +#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27) +#define NETBIRD_GPIO_LOAD GPIO_TO_PIN(1, 9) +/* TODO: Who configures UART0_RTSn, GPIO1_9 ? */ +#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 11) +#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10) static int shield_slot_initialized = 0; -/* V2OK */ -static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = { - /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ - {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E15) UART0_RXD */ - {OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E16) UART0_TXD */ +/* TODO: Naming -> config, final */ +static struct module_pin_mux shield_gpio_netbird_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)}, /* (E15) gpio1_10 */ /* Mode 0 */ + {OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (E16) gpio1_11 */ /* Mode 1 */ {-1}, }; -static struct module_pin_mux shield_gpio_netbird_pin_mux[] = { - /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ - {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)}, /* (E15) UART0_RXD */ - {OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (E16) UART0_TXD */ +static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = { + /* Leave UART0 unconfigured (GPIO) because we want to configure it as needed by linux (can/spi/uart/etc) */ + {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E15) gpio1_10 */ /* Mode 0 */ + {OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E16) gpio1_11 */ /* Mode 1 */ {-1}, }; + static int request_gpios(void) { int ret; @@ -153,8 +154,8 @@ struct mode { }; struct mode modes[] = { - {RS232, "rs232", 0}, - {RS485, "rs485", 2} + { RS232, "rs232", 0 }, + { RS485, "rs485", 2 } }; static const struct mode *get_mode(const char *mode) @@ -240,6 +241,7 @@ int set_shieldmode(char * const argv[], int argc) return configure_shieldmode(get_mode_from_args(argv, argc)); } +/* TODO: Static ? */ struct shield_t comio_shield = { "comio", set_shieldmode }; @@ -248,4 +250,3 @@ void comio_shield_init(void) { shield_register(&comio_shield); } -