dm: treewide: Rename ..._platdata variables to just ..._plat

Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>

arch/arm/include/asm/arch-hi6220/gpio.h

@@ -18,7 +18,7 @@ struct gpio_bank {
 };
 
 /* Information about a GPIO bank */
-struct hikey_gpio_platdata {
+struct hikey_gpio_plat {
 	int bank_index;
 	ulong base;     /* address of registers in physical memory */
 };

arch/arm/include/asm/arch-imx8/power-domain.h

@@ -8,7 +8,7 @@
 
 #include <asm/arch/sci/types.h>
 
-struct imx8_power_domain_platdata {
+struct imx8_power_domain_plat {
 	sc_rsrc_t resource_id;
 };
 

arch/arm/include/asm/arch-imx8m/power-domain.h

@@ -6,7 +6,7 @@
 #ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
 #define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
 
-struct imx8m_power_domain_platdata {
+struct imx8m_power_domain_plat {
 	int resource_id;
 	int has_pd;
 	struct power_domain pd;

arch/arm/include/asm/arch-vf610/gpio.h

@@ -20,7 +20,7 @@ struct vybrid_gpio_regs {
 	u32 gpio_pdir;
 };
 
-struct vybrid_gpio_platdata {
+struct vybrid_gpio_plat {
 	unsigned int chip;
 	u32 base;
 	const char *port_name;

arch/arm/include/asm/omap_gpio.h

@@ -25,7 +25,7 @@
 #if CONFIG_IS_ENABLED(DM_GPIO)
 
 /* Information about a GPIO bank */
-struct omap_gpio_platdata {
+struct omap_gpio_plat {
 	int bank_index;
 	ulong base;	/* address of registers in physical memory */
 	const char *port_name;

arch/arm/include/asm/omap_i2c.h

@@ -6,7 +6,7 @@
 #ifdef CONFIG_DM_I2C
 
 /* Information about a GPIO bank */
-struct omap_i2c_platdata {
+struct omap_i2c_plat {
 	ulong base;	/* address of registers in physical memory */
 	int speed;
 	int ip_rev;

arch/arm/include/asm/omap_musb.h

@@ -23,7 +23,7 @@ struct omap_musb_board_data {
 
 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 
-struct ti_musb_platdata {
+struct ti_musb_plat {
 	void *base;
 	void *ctrl_mod_base;
 	struct musb_hdrc_platform_data plat;

arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c

@@ -213,7 +213,7 @@ void at91_sdram_hw_init(void)
 }
 
 /* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
 	{ ATMEL_BASE_PIOA, "PA" },
 	{ ATMEL_BASE_PIOB, "PB" },
 	{ ATMEL_BASE_PIOC, "PC" },

arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c

@@ -167,7 +167,7 @@ void at91_mci_hw_init(void)
 #endif
 
 /* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
 	{ ATMEL_BASE_PIOA, "PA" },
 	{ ATMEL_BASE_PIOB, "PB" },
 	{ ATMEL_BASE_PIOC, "PC" },

arch/arm/mach-at91/include/mach/atmel_serial.h

@@ -7,7 +7,7 @@
 #define _ATMEL_SERIAL_H
 
 /* Information about a serial port */
-struct atmel_serial_platdata {
+struct atmel_serial_plat {
 	uint32_t base_addr;
 };
 

arch/arm/mach-at91/include/mach/gpio.h

@@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio)
 }
 
 /* Platform data for each GPIO port */
-struct at91_port_platdata {
+struct at91_port_plat {
 	uint32_t base_addr;
 	const char *bank_name;
 };

arch/arm/mach-bcm283x/include/mach/gpio.h

@@ -52,11 +52,11 @@ struct bcm2835_gpio_regs {
 };
 
 /**
- * struct bcm2835_gpio_platdata - GPIO platform description
+ * struct bcm2835_gpio_plat - GPIO platform description
  *
  * @base: Base address of GPIO controller
  */
-struct bcm2835_gpio_platdata {
+struct bcm2835_gpio_plat {
 	unsigned long base;
 };
 

arch/arm/mach-lpc32xx/devices.c

@@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
 }
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata lpc32xx_uart[] = {
+static const struct ns16550_plat lpc32xx_uart[] = {
 	{ .base = UART3_BASE, .reg_shift = 2,
 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 	{ .base = UART4_BASE, .reg_shift = 2,
@@ -55,7 +55,7 @@ static const struct ns16550_platdata lpc32xx_uart[] = {
 };
 
 #if defined(CONFIG_LPC32XX_HSUART)
-static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
 	{ HS_UART1_BASE, },
 	{ HS_UART2_BASE, },
 	{ HS_UART7_BASE, },

arch/arm/mach-nexell/include/mach/display.h

@@ -212,7 +212,7 @@ struct dp_hdmi_dev {
 };
 
 /* platform data for the driver model */
-struct nx_display_platdata {
+struct nx_display_plat {
 	int module;
 	struct dp_sync_info sync;
 	struct dp_ctrl_info ctrl;
@@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps);
 
 #if defined CONFIG_SPL_BUILD ||	\
 	(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
-int nx_display_probe(struct nx_display_platdata *plat);
+int nx_display_probe(struct nx_display_plat *plat);
 #endif
 
 #endif

arch/arm/mach-omap2/am33xx/board.c

@@ -80,7 +80,7 @@ int dram_init_banksize(void)
 }
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata am33xx_serial[] = {
+static const struct ns16550_plat am33xx_serial[] = {
 	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 # ifdef CONFIG_SYS_NS16550_COM2
@@ -113,7 +113,7 @@ U_BOOT_DEVICES(am33xx_uarts) = {
 };
 
 #ifdef CONFIG_DM_I2C
-static const struct omap_i2c_platdata am33xx_i2c[] = {
+static const struct omap_i2c_plat am33xx_i2c[] = {
 	{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
 	{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
 	{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
@@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
 #endif
 
 #if CONFIG_IS_ENABLED(DM_GPIO)
-static const struct omap_gpio_platdata am33xx_gpio[] = {
+static const struct omap_gpio_plat am33xx_gpio[] = {
 	{ 0, AM33XX_GPIO0_BASE },
 	{ 1, AM33XX_GPIO1_BASE },
 	{ 2, AM33XX_GPIO2_BASE },
@@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = {
 };
 
 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ti_musb_platdata usb0 = {
+static struct ti_musb_plat usb0 = {
 	.base = (void *)USB0_OTG_BASE,
 	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
 	.plat = {
@@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = {
 		},
 };
 
-static struct ti_musb_platdata usb1 = {
+static struct ti_musb_plat usb1 = {
 	.base = (void *)USB1_OTG_BASE,
 	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
 	.plat = {

arch/arm/mach-omap2/omap3/board.c

@@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void);
 #if CONFIG_IS_ENABLED(DM_GPIO)
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 /* Manually initialize GPIO banks when OF_CONTROL doesn't */
-static const struct omap_gpio_platdata omap34xx_gpio[] = {
+static const struct omap_gpio_plat omap34xx_gpio[] = {
 	{ 0, OMAP34XX_GPIO1_BASE },
 	{ 1, OMAP34XX_GPIO2_BASE },
 	{ 2, OMAP34XX_GPIO3_BASE },

arch/arm/mach-rockchip/px30/syscon_px30.c

@@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = {
 };
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int px30_syscon_bind_of_platdata(struct udevice *dev)
+static int px30_syscon_bind_of_plat(struct udevice *dev)
 {
 	dev->driver_data = dev->driver->of_match->data;
 	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = {
 	.name = "rockchip_px30_pmu",
 	.id = UCLASS_SYSCON,
 	.of_match = px30_syscon_ids,
-	.bind = px30_syscon_bind_of_platdata,
+	.bind = px30_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
 	.name = "rockchip_px30_pmugrf",
 	.id = UCLASS_SYSCON,
 	.of_match = px30_syscon_ids + 1,
-	.bind = px30_syscon_bind_of_platdata,
+	.bind = px30_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_px30_grf) = {
 	.name = "rockchip_px30_grf",
 	.id = UCLASS_SYSCON,
 	.of_match = px30_syscon_ids + 2,
-	.bind = px30_syscon_bind_of_platdata,
+	.bind = px30_syscon_bind_of_plat,
 };
 #endif

arch/arm/mach-rockchip/rk3188/syscon_rk3188.c

@@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = {
 };
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3188_syscon_bind_of_plat(struct udevice *dev)
 {
 	dev->driver_data = dev->driver->of_match->data;
 	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = {
 	.name = "rockchip_rk3188_noc",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3188_syscon_ids,
-	.bind = rk3188_syscon_bind_of_platdata,
+	.bind = rk3188_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3188_grf) = {
 	.name = "rockchip_rk3188_grf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3188_syscon_ids + 1,
-	.bind = rk3188_syscon_bind_of_platdata,
+	.bind = rk3188_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
 	.name = "rockchip_rk3188_pmu",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3188_syscon_ids + 2,
-	.bind = rk3188_syscon_bind_of_platdata,
+	.bind = rk3188_syscon_bind_of_plat,
 };
 #endif

arch/arm/mach-rockchip/rk3288/syscon_rk3288.c

@@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = {
 };
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3288_syscon_bind_of_plat(struct udevice *dev)
 {
 	dev->driver_data = dev->driver->of_match->data;
 	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = {
 	.name = "rockchip_rk3288_noc",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids,
-	.bind = rk3288_syscon_bind_of_platdata,
+	.bind = rk3288_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3288_grf) = {
 	.name = "rockchip_rk3288_grf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids + 1,
-	.bind = rk3288_syscon_bind_of_platdata,
+	.bind = rk3288_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
 	.name = "rockchip_rk3288_sgrf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids + 2,
-	.bind = rk3288_syscon_bind_of_platdata,
+	.bind = rk3288_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
 	.name = "rockchip_rk3288_pmu",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids + 3,
-	.bind = rk3288_syscon_bind_of_platdata,
+	.bind = rk3288_syscon_bind_of_plat,
 };
 #endif

arch/arm/mach-rockchip/rk3368/syscon_rk3368.c

@@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = {
 };
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3368_syscon_bind_of_plat(struct udevice *dev)
 {
 	dev->driver_data = dev->driver->of_match->data;
 	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = {
 	.name = "rockchip_rk3368_grf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids,
-	.bind = rk3368_syscon_bind_of_platdata,
+	.bind = rk3368_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
 	.name = "rockchip_rk3368_pmugrf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids + 1,
-	.bind = rk3368_syscon_bind_of_platdata,
+	.bind = rk3368_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3368_msch) = {
 	.name = "rockchip_rk3368_msch",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids + 2,
-	.bind = rk3368_syscon_bind_of_platdata,
+	.bind = rk3368_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
 	.name = "rockchip_rk3368_sgrf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids + 3,
-	.bind = rk3368_syscon_bind_of_platdata,
+	.bind = rk3368_syscon_bind_of_plat,
 };
 #endif

arch/arm/mach-rockchip/rk3399/syscon_rk3399.c

@@ -28,7 +28,7 @@ U_BOOT_DRIVER(syscon_rk3399) = {
 };
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3399_syscon_bind_of_plat(struct udevice *dev)
 {
 	dev->driver_data = dev->driver->of_match->data;
 	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@@ -40,34 +40,34 @@ U_BOOT_DRIVER(rockchip_rk3399_grf) = {
 	.name = "rockchip_rk3399_grf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3399_syscon_ids,
-	.bind = rk3399_syscon_bind_of_platdata,
+	.bind = rk3399_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
 	.name = "rockchip_rk3399_pmugrf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3399_syscon_ids + 1,
-	.bind = rk3399_syscon_bind_of_platdata,
+	.bind = rk3399_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
 	.name = "rockchip_rk3399_pmusgrf",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3399_syscon_ids + 2,
-	.bind = rk3399_syscon_bind_of_platdata,
+	.bind = rk3399_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3399_cic) = {
 	.name = "rockchip_rk3399_cic",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3399_syscon_ids + 3,
-	.bind = rk3399_syscon_bind_of_platdata,
+	.bind = rk3399_syscon_bind_of_plat,
 };
 
 U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
 	.name = "rockchip_rk3399_pmu",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3399_syscon_ids + 4,
-	.bind = rk3399_syscon_bind_of_platdata,
+	.bind = rk3399_syscon_bind_of_plat,
 };
 #endif

arch/arm/mach-stm32mp/bsec.c

@@ -280,13 +280,13 @@ static int bsec_program_otp(long base, u32 val, u32 otp)
 }
 
 /* BSEC MISC driver *******************************************************/
-struct stm32mp_bsec_platdata {
+struct stm32mp_bsec_plat {
 	u32 base;
 };
 
 static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
 {
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 	u32 tmp_data = 0;
 	int ret;
 
@@ -319,7 +319,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
 
 static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
 {
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 
 	if (IS_ENABLED(CONFIG_TFABOOT))
 		return stm32_smc(STM32_SMC_BSEC,
@@ -333,7 +333,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
 
 static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
 {
-	struct stm32mp_bsec_platdata *plat = dev_get_plat(dev);
+	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
 
 	/* return OTP permanent write lock status */
 	*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
@@ -343,7 +343,7 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
 
 static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
 {
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 
 	if (IS_ENABLED(CONFIG_TFABOOT))
 		return stm32_smc_exec(STM32_SMC_BSEC,
@@ -358,7 +358,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
 
 static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
 {
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 
 	if (IS_ENABLED(CONFIG_TFABOOT))
 		return stm32_smc_exec(STM32_SMC_BSEC,
@@ -475,7 +475,7 @@ static const struct misc_ops stm32mp_bsec_ops = {
 
 static int stm32mp_bsec_of_to_plat(struct udevice *dev)
 {
-	struct stm32mp_bsec_platdata *plat = dev_get_plat(dev);
+	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
 
 	plat->base = (u32)dev_read_addr_ptr(dev);
 
@@ -485,7 +485,7 @@ static int stm32mp_bsec_of_to_plat(struct udevice *dev)
 static int stm32mp_bsec_probe(struct udevice *dev)
 {
 	int otp;
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 
 	/*
 	 * update unlocked shadow for OTP cleared by the rom code
@@ -513,7 +513,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
 	.id = UCLASS_MISC,
 	.of_match = stm32mp_bsec_ids,
 	.of_to_plat = stm32mp_bsec_of_to_plat,
-	.plat_auto	= sizeof(struct stm32mp_bsec_platdata),
+	.plat_auto	= sizeof(struct stm32mp_bsec_plat),
 	.ops = &stm32mp_bsec_ops,
 	.probe = stm32mp_bsec_probe,
 };
@@ -521,7 +521,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
 bool bsec_dbgswenable(void)
 {
 	struct udevice *dev;
-	struct stm32mp_bsec_platdata *plat;
+	struct stm32mp_bsec_plat *plat;
 	int ret;
 
 	ret = uclass_get_device_by_driver(UCLASS_MISC,

arch/arm/mach-tegra/board.c

@@ -257,7 +257,7 @@ void board_init_uart_f(void)
 }
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ns16550_platdata ns16550_com1_pdata = {
+static struct ns16550_plat ns16550_com1_pdata = {
 	.base = CONFIG_SYS_NS16550_COM1,
 	.reg_shift = 2,
 	.clock = CONFIG_SYS_NS16550_CLK,

arch/riscv/include/asm/arch-fu540/gpio.h

@@ -28,7 +28,7 @@ enum gpio_state {
 };
 
 /* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
 	void *base;     /* address of registers in physical memory */
 };
 

arch/riscv/include/asm/arch-generic/gpio.h

@@ -28,7 +28,7 @@ enum gpio_state {
 };
 
 /* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
 	void *base;     /* address of registers in physical memory */
 };
 

arch/x86/cpu/apollolake/hostbridge.c

@@ -42,7 +42,7 @@ enum {
 };
 
 /**
- * struct apl_hostbridge_platdata - platform data for hostbridge
+ * struct apl_hostbridge_plat - platform data for hostbridge
  *
  * @dtplat: Platform data for of-platdata
  * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
@@ -50,7 +50,7 @@ enum {
  * @pciex_region_size: BAR length in bytes
  * @bdf: Bus/device/function of hostbridge
  */
-struct apl_hostbridge_platdata {
+struct apl_hostbridge_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_apl_hostbridge dtplat;
 #endif
@@ -158,7 +158,7 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
 
 static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
 {
-	struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+	struct apl_hostbridge_plat *plat = dev_get_plat(dev);
 	struct udevice *pinctrl;
 	int ret;
 
@@ -172,7 +172,7 @@ static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
 
 static int apl_hostbridge_early_init(struct udevice *dev)
 {
-	struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+	struct apl_hostbridge_plat *plat = dev_get_plat(dev);
 	u32 region_size;
 	ulong base;
 	u32 reg;
@@ -223,7 +223,7 @@ static int apl_hostbridge_early_init(struct udevice *dev)
 
 static int apl_hostbridge_of_to_plat(struct udevice *dev)
 {
-	struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+	struct apl_hostbridge_plat *plat = dev_get_plat(dev);
 	struct udevice *pinctrl;
 	int ret;
 
@@ -403,7 +403,7 @@ U_BOOT_DRIVER(intel_apl_hostbridge) = {
 	.of_to_plat = apl_hostbridge_of_to_plat,
 	.probe		= apl_hostbridge_probe,
 	.remove		= apl_hostbridge_remove,
-	.plat_auto	= sizeof(struct apl_hostbridge_platdata),
+	.plat_auto	= sizeof(struct apl_hostbridge_plat),
 	ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
 	.flags		= DM_FLAG_OS_PREPARE,
 };

arch/x86/cpu/apollolake/pmc.c

@@ -53,7 +53,7 @@ enum {
 	CF9_GLB_RST	= 1 << 20,
 };
 
-struct apl_pmc_platdata {
+struct apl_pmc_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_apl_pmc dtplat;
 #endif
@@ -108,10 +108,10 @@ static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
 	return 0;
 }
 
-int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
+int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
 {
 	struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
-	struct apl_pmc_platdata *plat = dev_get_plat(dev);
+	struct apl_pmc_plat *plat = dev_get_plat(dev);
 
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	u32 base[6];
@@ -144,7 +144,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
 	if (ret)
 		return log_msg_ret("Bad gpe0-dw", ret);
 
-	return pmc_ofdata_to_uc_platdata(dev);
+	return pmc_ofdata_to_uc_plat(dev);
 #else
 	struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
 
@@ -169,7 +169,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
 static int enable_pmcbar(struct udevice *dev)
 {
 	struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
-	struct apl_pmc_platdata *priv = dev_get_plat(dev);
+	struct apl_pmc_plat *priv = dev_get_plat(dev);
 	pci_dev_t pmc = priv->bdf;
 
 	/*
@@ -221,8 +221,8 @@ U_BOOT_DRIVER(intel_apl_pmc) = {
 	.name		= "intel_apl_pmc",
 	.id		= UCLASS_ACPI_PMC,
 	.of_match	= apl_pmc_ids,
-	.of_to_plat = apl_pmc_ofdata_to_uc_platdata,
+	.of_to_plat = apl_pmc_ofdata_to_uc_plat,
 	.probe		= apl_pmc_probe,
 	.ops		= &apl_pmc_ops,
-	.plat_auto	= sizeof(struct apl_pmc_platdata),
+	.plat_auto	= sizeof(struct apl_pmc_plat),
 };

arch/x86/cpu/apollolake/spl.c

@@ -92,7 +92,7 @@ static int apl_flash_bind(struct udevice *dev)
 {
 	if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
 	    !CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
-		struct dm_spi_slave_platdata *plat;
+		struct dm_spi_slave_plat *plat;
 		struct udevice *spi;
 		int ret;
 

arch/x86/cpu/apollolake/uart.c

@@ -68,7 +68,7 @@ void apl_uart_init(pci_dev_t bdf, ulong base)
  * This driver uses its own compatible string but almost everything else from
  * the standard ns16550 driver. This allows us to provide an of-platdata
  * implementation, since the platdata produced by of-platdata does not match
- * struct ns16550_platdata.
+ * struct ns16550_plat.
  *
  * When running with of-platdata (generally TPL), the platdata is converted to
  * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
@@ -77,7 +77,7 @@ void apl_uart_init(pci_dev_t bdf, ulong base)
 
 static int apl_ns16550_probe(struct udevice *dev)
 {
-	struct ns16550_platdata *plat = dev_get_plat(dev);
+	struct ns16550_plat *plat = dev_get_plat(dev);
 
 	if (!CONFIG_IS_ENABLED(PCI))
 		apl_uart_init(plat->bdf, plat->base);
@@ -89,7 +89,7 @@ static int apl_ns16550_of_to_plat(struct udevice *dev)
 {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
-	struct ns16550_platdata *plat;
+	struct ns16550_plat *plat;
 
 	/*
 	 * Convert our plat to the ns16550's plat, so we can just use
@@ -126,7 +126,7 @@ U_BOOT_DRIVER(intel_apl_ns16550) = {
 	.name	= "intel_apl_ns16550",
 	.id	= UCLASS_SERIAL,
 	.of_match = apl_ns16550_serial_ids,
-	.plat_auto	= sizeof(struct ns16550_platdata),
+	.plat_auto	= sizeof(struct ns16550_plat),
 	.priv_auto	= sizeof(struct NS16550),
 	.ops	= &ns16550_serial_ops,
 	.of_to_plat = apl_ns16550_of_to_plat,

arch/x86/cpu/broadwell/sata.c

@@ -17,7 +17,7 @@
 #include <asm/arch/pch.h>
 #include <linux/delay.h>
 
-struct sata_platdata {
+struct sata_plat {
 	int port_map;
 	uint port0_gen3_tx;
 	uint port1_gen3_tx;
@@ -41,7 +41,7 @@ struct sata_platdata {
 
 static void broadwell_sata_init(struct udevice *dev)
 {
-	struct sata_platdata *plat = dev_get_plat(dev);
+	struct sata_plat *plat = dev_get_plat(dev);
 	u32 reg32;
 	u8 *abar;
 	u16 reg16;
@@ -211,7 +211,7 @@ static void broadwell_sata_init(struct udevice *dev)
 
 static int broadwell_sata_enable(struct udevice *dev)
 {
-	struct sata_platdata *plat = dev_get_plat(dev);
+	struct sata_plat *plat = dev_get_plat(dev);
 	struct gpio_desc desc;
 	u16 map;
 	int ret;
@@ -234,7 +234,7 @@ static int broadwell_sata_enable(struct udevice *dev)
 
 static int broadwell_sata_of_to_plat(struct udevice *dev)
 {
-	struct sata_platdata *plat = dev_get_plat(dev);
+	struct sata_plat *plat = dev_get_plat(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev_of_offset(dev);
 
@@ -266,5 +266,5 @@ U_BOOT_DRIVER(ahci_broadwell_drv) = {
 	.of_match	= broadwell_ahci_ids,
 	.of_to_plat	= broadwell_sata_of_to_plat,
 	.probe		= broadwell_sata_probe,
-	.plat_auto	 = sizeof(struct sata_platdata),
+	.plat_auto	 = sizeof(struct sata_plat),
 };

arch/x86/cpu/cpu_x86.c

@@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int cpu_x86_bind(struct udevice *dev)
 {
-	struct cpu_platdata *plat = dev_get_parent_plat(dev);
+	struct cpu_plat *plat = dev_get_parent_plat(dev);
 	struct cpuid_result res;
 
 	plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),

arch/x86/cpu/intel_common/itss.c

@@ -19,7 +19,7 @@
 #include <spl.h>
 #include <asm/itss.h>
 
-struct itss_platdata {
+struct itss_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	/* Put this first since driver model will copy the data here */
 	struct dtd_intel_itss dtplat;
@@ -184,7 +184,7 @@ static int itss_of_to_plat(struct udevice *dev)
 	int ret;
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct itss_platdata *plat = dev_get_plat(dev);
+	struct itss_plat *plat = dev_get_plat(dev);
 	struct dtd_intel_itss *dtplat = &plat->dtplat;
 
 	/*
@@ -242,6 +242,6 @@ U_BOOT_DRIVER(intel_itss) = {
 	.ops		= &itss_ops,
 	.bind		= itss_bind,
 	.of_to_plat = itss_of_to_plat,
-	.plat_auto	= sizeof(struct itss_platdata),
+	.plat_auto	= sizeof(struct itss_plat),
 	.priv_auto	= sizeof(struct itss_priv),
 };

arch/x86/cpu/intel_common/p2sb.c

@@ -19,7 +19,7 @@
 #define PCH_P2SB_E0		0xe0
 #define HIDE_BIT		BIT(0)
 
-struct p2sb_platdata {
+struct p2sb_plat {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_p2sb dtplat;
 #endif
@@ -57,7 +57,7 @@ struct p2sb_platdata {
  */
 static int p2sb_early_init(struct udevice *dev)
 {
-	struct p2sb_platdata *plat = dev_get_plat(dev);
+	struct p2sb_plat *plat = dev_get_plat(dev);
 	pci_dev_t pdev = plat->bdf;
 
 	/*
@@ -93,7 +93,7 @@ static int p2sb_spl_init(struct udevice *dev)
 int p2sb_of_to_plat(struct udevice *dev)
 {
 	struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
-	struct p2sb_platdata *plat = dev_get_plat(dev);
+	struct p2sb_plat *plat = dev_get_plat(dev);
 
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	int ret;
@@ -167,7 +167,7 @@ static int p2sb_remove(struct udevice *dev)
 static int p2sb_child_post_bind(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+	struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
 	int ret;
 	u32 pid;
 
@@ -197,8 +197,8 @@ U_BOOT_DRIVER(intel_p2sb) = {
 	.remove		= p2sb_remove,
 	.ops		= &p2sb_ops,
 	.of_to_plat = p2sb_of_to_plat,
-	.plat_auto	= sizeof(struct p2sb_platdata),
+	.plat_auto	= sizeof(struct p2sb_plat),
-	.per_child_plat_auto	= sizeof(struct p2sb_child_platdata),
+	.per_child_plat_auto	= sizeof(struct p2sb_child_plat),
 	.child_post_bind = p2sb_child_post_bind,
 	.flags		= DM_FLAG_OS_PREPARE,
 };

arch/x86/cpu/mp_init.c

@@ -221,7 +221,7 @@ static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_plat(dev);
+		struct cpu_plat *plat = dev_get_parent_plat(dev);
 
 		if (plat->cpu_id == apic_id) {
 			*devp = dev;
@@ -706,7 +706,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused)
 
 static int mp_init_cpu(struct udevice *cpu, void *unused)
 {
-	struct cpu_platdata *plat = dev_get_parent_plat(cpu);
+	struct cpu_plat *plat = dev_get_parent_plat(cpu);
 
 	plat->ucode_version = microcode_read_rev();
 	plat->device_id = gd->arch.x86_device;

arch/x86/cpu/qfw_cpu.c

@@ -18,7 +18,7 @@ int qemu_cpu_fixup(void)
 	int cpu_num;
 	int cpu_online;
 	struct udevice *dev, *pdev;
-	struct cpu_platdata *plat;
+	struct cpu_plat *plat;
 	char *cpu;
 
 	/* first we need to find '/cpus' */

arch/x86/cpu/slimbootloader/serial.c

@@ -18,7 +18,7 @@ static int slimbootloader_serial_of_to_plat(struct udevice *dev)
 {
 	const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
 	struct sbl_serial_port_info *data;
-	struct ns16550_platdata *plat = dev->plat;
+	struct ns16550_plat *plat = dev->plat;
 
 	if (!gd->arch.hob_list)
 		panic("hob list not found!");
@@ -58,7 +58,7 @@ U_BOOT_DRIVER(serial_slimbootloader) = {
 	.id	= UCLASS_SERIAL,
 	.of_match = slimbootloader_serial_ids,
 	.of_to_plat = slimbootloader_serial_of_to_plat,
-	.plat_auto	= sizeof(struct ns16550_platdata),
+	.plat_auto	= sizeof(struct ns16550_plat),
 	.priv_auto	= sizeof(struct NS16550),
 	.probe	= ns16550_serial_probe,
 	.ops	= &ns16550_serial_ops,

arch/x86/include/asm/arch-broadwell/gpio.h

@@ -11,7 +11,7 @@
 #define GPIO_PER_BANK	32
 #define GPIO_BANKS	3
 
-struct broadwell_bank_platdata {
+struct broadwell_bank_plat {
 	uint16_t base_addr;
 	const char *bank_name;
 	int bank;

arch/x86/include/asm/gpio.h

@@ -8,7 +8,7 @@
 
 #include <asm-generic/gpio.h>
 
-struct ich6_bank_platdata {
+struct ich6_bank_plat {
 	uint16_t base_addr;
 	const char *bank_name;
 	int offset;

arch/x86/lib/acpi_table.c

@@ -74,7 +74,7 @@ int acpi_create_madt_lapics(u32 current)
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_plat(dev);
+		struct cpu_plat *plat = dev_get_parent_plat(dev);
 		int length;
 
 		length = acpi_create_madt_lapic(

arch/x86/lib/fsp/fsp_graphics.c

@@ -80,7 +80,7 @@ static int save_vesa_mode(struct vesa_mode_info *vesa)
 
 static int fsp_video_probe(struct udevice *dev)
 {
-	struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct vesa_mode_info *vesa = &mode_info.vesa;
 	int ret;
@@ -124,7 +124,7 @@ err:
 
 static int fsp_video_bind(struct udevice *dev)
 {
-	struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
 
 	/* Set the maximum supported resolution */
 	plat->size = 2560 * 1600 * 4;

arch/x86/lib/mpspec.c

@@ -81,7 +81,7 @@ void mp_write_processor(struct mp_config_table *mc)
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_plat(dev);
+		struct cpu_plat *plat = dev_get_parent_plat(dev);
 		u8 cpuflag = MPC_CPU_EN;
 
 		if (!device_active(dev))

arch/x86/lib/sfi.c

@@ -84,7 +84,7 @@ static int sfi_write_cpus(struct table_info *tab)
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_plat(dev);
+		struct cpu_plat *plat = dev_get_parent_plat(dev);
 
 		if (!device_active(dev))
 			continue;

board/armltd/integrator/integrator.c

@@ -32,7 +32,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = 0x16000000,
 #ifdef CONFIG_ARCH_CINTEGRATOR
 	.type = TYPE_PL011,
@@ -45,7 +45,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(integrator_serials) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 
 void peripheral_power_enable (void);

board/armltd/total_compute/total_compute.c

@@ -9,7 +9,7 @@
 #include <dm/platform_data/serial_pl01x.h>
 #include <asm/armv8/mmu.h>
 
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = UART0_BASE,
 	.type = TYPE_PL011,
 	.clock = CONFIG_PL011_CLOCK,
@@ -17,7 +17,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(total_compute_serials) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 
 static struct mm_region total_compute_mem_map[] = {

board/armltd/vexpress64/vexpress64.c

@@ -20,7 +20,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = V2M_UART0,
 	.type = TYPE_PL011,
 	.clock = CONFIG_PL011_CLOCK,
@@ -28,7 +28,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(vexpress_serials) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 
 static struct mm_region vexpress64_mem_map[] = {

board/bluewater/gurnard/gurnard.c

@@ -348,7 +348,7 @@ int board_init(void)
 
 		uclass_find_first_device(UCLASS_VIDEO, &dev);
 		if (dev) {
-			struct atmel_lcd_platdata *plat = dev_get_plat(dev);
+			struct atmel_lcd_plat *plat = dev_get_plat(dev);
 
 			plat->timing_index = 1;
 		}
@@ -416,7 +416,7 @@ void reset_phy(void)
 {
 }
 
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
 	.base_addr = ATMEL_BASE_DBGU,
 };
 

board/bluewater/snapper9260/snapper9260.c

@@ -143,7 +143,7 @@ void reset_phy(void)
 {
 }
 
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
 	.base_addr = ATMEL_BASE_DBGU,
 };
 

board/cavium/thunderx/thunderx.c

@@ -18,7 +18,7 @@
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 #include <dm/platform_data/serial_pl01x.h>
 
-static const struct pl01x_serial_platdata serial0 = {
+static const struct pl01x_serial_plat serial0 = {
 	.base = CONFIG_SYS_SERIAL0,
 	.type = TYPE_PL011,
 	.clock = 0,
@@ -30,7 +30,7 @@ U_BOOT_DEVICE(thunderx_serial0) = {
 	.plat = &serial0,
 };
 
-static const struct pl01x_serial_platdata serial1 = {
+static const struct pl01x_serial_plat serial1 = {
 	.base = CONFIG_SYS_SERIAL1,
 	.type = TYPE_PL011,
 	.clock = 0,

board/compulab/cm_fx6/cm_fx6.c

@@ -724,7 +724,7 @@ u32 get_board_rev(void)
 	return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
 }
 
-static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
+static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART4_BASE,
 };
 

board/davinci/da8xxevm/omapl138_lcdk.c

@@ -356,7 +356,7 @@ int board_mmc_init(struct bd_info *bis)
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata serial_pdata = {
+static const struct ns16550_plat serial_pdata = {
 	.base = DAVINCI_UART2_BASE,
 	.reg_shift = 2,
 	.clock = 228000000,
@@ -368,7 +368,7 @@ U_BOOT_DEVICE(omapl138_uart) = {
 	.plat = &serial_pdata,
 };
 
-static const struct davinci_mmc_plat mmc_platdata = {
+static const struct davinci_mmc_plat mmc_plat = {
 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
 	.cfg = {
 		.f_min = 200000,
@@ -381,7 +381,7 @@ static const struct davinci_mmc_plat mmc_platdata = {
 };
 U_BOOT_DEVICE(omapl138_mmc) = {
 	.name = "ti_da830_mmc",
-	.plat = &mmc_platdata,
+	.plat = &mmc_plat,
 };
 
 void spl_board_init(void)

board/freescale/lx2160a/lx2160a.c

@@ -51,7 +51,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl01x_serial_platdata serial0 = {
+static struct pl01x_serial_plat serial0 = {
 #if CONFIG_CONS_INDEX == 0
 	.base = CONFIG_SYS_SERIAL0,
 #elif CONFIG_CONS_INDEX == 1
@@ -67,7 +67,7 @@ U_BOOT_DEVICE(nxp_serial0) = {
 	.plat = &serial0,
 };
 
-static struct pl01x_serial_platdata serial1 = {
+static struct pl01x_serial_plat serial1 = {
 	.base = CONFIG_SYS_SERIAL1,
 	.type = TYPE_PL011,
 };

board/gateworks/gw_ventana/gw_ventana.c

@@ -1371,7 +1371,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
 
-static struct mxc_serial_platdata ventana_mxc_serial_plat = {
+static struct mxc_serial_plat ventana_mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART2_BASE,
 };
 

board/hisilicon/hikey/hikey.c

@@ -26,7 +26,7 @@
 #include <asm/armv8/mmu.h>
 
 /*TODO drop this table in favour of device tree */
-static const struct hikey_gpio_platdata hi6220_gpio[] = {
+static const struct hikey_gpio_plat hi6220_gpio[] = {
 	{ 0, HI6220_GPIO_BASE(0)},
 	{ 1, HI6220_GPIO_BASE(1)},
 	{ 2, HI6220_GPIO_BASE(2)},
@@ -77,7 +77,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 #if CONFIG_CONS_INDEX == 1
 	.base = HI6220_UART0_BASE,
 #elif CONFIG_CONS_INDEX == 4
@@ -91,7 +91,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(hikey_seriala) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 #endif
 

board/hisilicon/hikey960/hikey960.c

@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 #include <dm/platform_data/serial_pl01x.h>
 
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = HI3660_UART6_BASE,
 	.type = TYPE_PL011,
 	.clock = 19200000
@@ -34,7 +34,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(hikey960_serial0) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 #endif
 

board/hisilicon/poplar/poplar.c

@@ -40,7 +40,7 @@ static struct mm_region poplar_mem_map[] = {
 struct mm_region *mem_map = poplar_mem_map;
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = REG_BASE_UART0,
 	.type = TYPE_PL010,
 	.clock = 75000000,
@@ -48,7 +48,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(poplar_serial) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 #endif
 

board/isee/igep00x0/igep00x0.c

@@ -29,7 +29,7 @@
 #include <fdt_support.h>
 #include "igep00x0.h"
 
-static const struct ns16550_platdata igep_serial = {
+static const struct ns16550_plat igep_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
 	.clock = V_NS16550_CLK,

board/lg/sniper/sniper.c

@@ -30,7 +30,7 @@ const omap3_sysinfo sysinfo = {
 	.nand_string = "MMC"
 };
 
-static const struct ns16550_platdata serial_omap_platdata = {
+static const struct ns16550_plat serial_omap_plat = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
 	.clock = V_NS16550_CLK,
@@ -39,7 +39,7 @@ static const struct ns16550_platdata serial_omap_platdata = {
 
 U_BOOT_DEVICE(sniper_serial) = {
 	.name = "ns16550_serial",
-	.plat = &serial_omap_platdata
+	.plat = &serial_omap_plat
 };
 
 static struct musb_hdrc_config musb_config = {

board/nokia/rx51/rx51.c

@@ -703,7 +703,7 @@ void board_mmc_power_init(void)
 	twl4030_power_mmc_init(1);
 }
 
-static const struct omap_i2c_platdata rx51_i2c[] = {
+static const struct omap_i2c_plat rx51_i2c[] = {
 	{ I2C_BASE1, 2200000, OMAP_I2C_REV_V1 },
 	{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
 	{ I2C_BASE3, 400000, OMAP_I2C_REV_V1 },

board/siemens/corvus/board.c

@@ -314,7 +314,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	}
 }
 
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
 	.base_addr = ATMEL_BASE_DBGU,
 };
 

board/st/stv0991/stv0991.c

@@ -24,7 +24,7 @@ struct gpio_regs *const gpioa_regs =
 		(struct gpio_regs *) GPIOA_BASE_ADDR;
 
 #ifndef CONFIG_OF_CONTROL
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
 	.base = 0x80406000,
 	.type = TYPE_PL011,
 	.clock = 2700 * 1000,
@@ -32,7 +32,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(stv09911_serials) = {
 	.name = "serial_pl01x",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };
 #endif
 

board/sysam/amcore/amcore.c

@@ -107,7 +107,7 @@ int dram_init(void)
 	return 0;
 }
 
-static struct coldfire_serial_platdata mcf5307_serial_plat = {
+static struct coldfire_serial_plat mcf5307_serial_plat = {
 	.base = CONFIG_SYS_UART_BASE,
 	.port = 0,
 	.baudrate = CONFIG_BAUDRATE,

board/ti/am335x/board.c

@@ -963,7 +963,7 @@ void board_fit_image_post_process(void **p_image, size_t *p_size)
 #endif
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc0_plat = {
 	.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 	.cfg.f_min = 400000,
@@ -974,10 +974,10 @@ static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 
 U_BOOT_DEVICE(am335x_mmc0) = {
 	.name = "omap_hsmmc",
-	.plat = &am335x_mmc0_platdata,
+	.plat = &am335x_mmc0_plat,
 };
 
-static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc1_plat = {
 	.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 	.cfg.f_min = 400000,
@@ -988,6 +988,6 @@ static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 
 U_BOOT_DEVICE(am335x_mmc1) = {
 	.name = "omap_hsmmc",
-	.plat = &am335x_mmc1_platdata,
+	.plat = &am335x_mmc1_plat,
 };
 #endif

board/timll/devkit8000/devkit8000.c

@@ -47,7 +47,7 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
 	0
 };
 
-static const struct ns16550_platdata devkit8000_serial = {
+static const struct ns16550_plat devkit8000_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
 	.clock = V_NS16550_CLK,

board/toradex/apalis_imx6/apalis_imx6.c

@@ -1144,7 +1144,7 @@ void reset_cpu(ulong addr)
 
 #endif /* CONFIG_SPL_BUILD */
 
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
 	.use_dte = true,
 };

board/toradex/colibri-imx6ull/colibri-imx6ull.c

@@ -203,7 +203,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 }
 #endif
 
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
 	.use_dte = 1,
 };

board/toradex/colibri_imx6/colibri_imx6.c

@@ -1086,7 +1086,7 @@ void reset_cpu(ulong addr)
 
 #endif /* CONFIG_SPL_BUILD */
 
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
 	.use_dte = true,
 };

board/toradex/colibri_pxa270/colibri_pxa270.c

@@ -129,18 +129,18 @@ int board_mmc_init(struct bd_info *bis)
 	return 0;
 }
 #else /* !CONFIG_IS_ENABLED(DM_MMC) */
-static const struct pxa_mmc_plat mmc_platdata = {
+static const struct pxa_mmc_plat mmc_plat = {
 	.base = (struct pxa_mmc_regs *)MMC0_BASE,
 };
 
 U_BOOT_DEVICE(pxa_mmcs) = {
 	.name = "pxa_mmc",
-	.plat = &mmc_platdata,
+	.plat = &mmc_plat,
 };
 #endif /* !CONFIG_IS_ENABLED(DM_MMC) */
 #endif
 
-static const struct pxa_serial_platdata serial_platdata = {
+static const struct pxa_serial_plat serial_plat = {
 	.base = (struct pxa_uart_regs *)FFUART_BASE,
 	.port = FFUART_INDEX,
 	.baudrate = CONFIG_BAUDRATE,
@@ -148,5 +148,5 @@ static const struct pxa_serial_platdata serial_platdata = {
 
 U_BOOT_DEVICE(pxa_serials) = {
 	.name = "serial_pxa",
-	.plat = &serial_platdata,
+	.plat = &serial_plat,
 };

cmd/cpu.c

@@ -26,7 +26,7 @@ static int print_cpu_list(bool detail)
 	for (uclass_first_device(UCLASS_CPU, &dev);
 		     dev;
 		     uclass_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_plat(dev);
+		struct cpu_plat *plat = dev_get_parent_plat(dev);
 		struct cpu_info info;
 		bool first = true;
 		int ret, i;

cmd/pci.c

@@ -339,7 +339,7 @@ static void pciinfo(struct udevice *bus, bool short_listing)
 	for (device_find_first_child(bus, &dev);
 	     dev;
 	     device_find_next_child(&dev)) {
-		struct pci_child_platdata *pplat;
+		struct pci_child_plat *pplat;
 
 		pplat = dev_get_parent_plat(dev);
 		if (short_listing) {

cmd/regulator.c

@@ -55,9 +55,9 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	return CMD_RET_SUCCESS;
 }
 
-static int curr_dev_and_platdata(struct udevice **devp,
+static int curr_dev_and_plat(struct udevice **devp,
-				 struct dm_regulator_uclass_plat **uc_pdata,
+			     struct dm_regulator_uclass_plat **uc_pdata,
-				 bool allow_type_fixed)
+			     bool allow_type_fixed)
 {
 	*devp = NULL;
 	*uc_pdata = NULL;
@@ -150,7 +150,7 @@ static int do_info(struct cmd_tbl *cmdtp, int flag, int argc,
 	int ret;
 	int i;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, true);
 	if (ret)
 		return ret;
 
@@ -242,7 +242,7 @@ static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	int ret;
 
 	if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) {
-		ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+		ret = curr_dev_and_plat(&dev, &uc_pdata, true);
 		if (ret)
 			return CMD_RET_FAILURE;
 		do_status_detail(dev, uc_pdata);
@@ -268,7 +268,7 @@ static int do_value(struct cmd_tbl *cmdtp, int flag, int argc,
 	int force;
 	int ret;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
 	if (ret)
 		return ret;
 
@@ -317,7 +317,7 @@ static int do_current(struct cmd_tbl *cmdtp, int flag, int argc,
 	int current;
 	int ret;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
 	if (ret)
 		return ret;
 
@@ -357,7 +357,7 @@ static int do_mode(struct cmd_tbl *cmdtp, int flag, int argc,
 	int mode;
 	int ret;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, false);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, false);
 	if (ret)
 		return ret;
 
@@ -392,7 +392,7 @@ static int do_enable(struct cmd_tbl *cmdtp, int flag, int argc,
 	struct dm_regulator_uclass_plat *uc_pdata;
 	int ret;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, true);
 	if (ret)
 		return ret;
 
@@ -412,7 +412,7 @@ static int do_disable(struct cmd_tbl *cmdtp, int flag, int argc,
 	struct dm_regulator_uclass_plat *uc_pdata;
 	int ret;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+	ret = curr_dev_and_plat(&dev, &uc_pdata, true);
 	if (ret)
 		return ret;
 

common/lcd_simplefb.c

@@ -22,7 +22,7 @@ static int lcd_dt_simplefb_configure_node(void *blob, int off)
 	const char *name;
 	ulong fb_base;
 #ifdef CONFIG_DM_VIDEO
-	struct video_uc_platdata *plat;
+	struct video_uc_plat *plat;
 	struct video_priv *uc_priv;
 	struct udevice *dev;
 	int ret;

common/usb_hub.c

@@ -959,7 +959,7 @@ UCLASS_DRIVER(usb_hub) = {
 	.post_probe	= usb_hub_post_probe,
 	.child_pre_probe	= usb_child_pre_probe,
 	.per_child_auto	= sizeof(struct usb_device),
-	.per_child_plat_auto	= sizeof(struct usb_dev_platdata),
+	.per_child_plat_auto	= sizeof(struct usb_dev_plat),
 	.per_device_auto	= sizeof(struct usb_hub_device),
 };
 

doc/driver-model/of-plat.rst

@@ -242,7 +242,7 @@ For example:
 
     #include <dt-structs.h>
 
-    struct mmc_platdata {
+    struct mmc_plat {
     #if CONFIG_IS_ENABLED(OF_PLATDATA)
             /* Put this first since driver model will copy the data here */
             struct dtd_mmc dtplat;
@@ -258,7 +258,7 @@ For example:
     {
     #if !CONFIG_IS_ENABLED(OF_PLATDATA)
             /* Decode the device tree data */
-            struct mmc_platdata *plat = dev_get_plat(dev);
+            struct mmc_plat *plat = dev_get_plat(dev);
             const void *blob = gd->fdt_blob;
             int node = dev_of_offset(dev);
 
@@ -270,7 +270,7 @@ For example:
 
     static int mmc_probe(struct udevice *dev)
     {
-            struct mmc_platdata *plat = dev_get_plat(dev);
+            struct mmc_plat *plat = dev_get_plat(dev);
 
     #if CONFIG_IS_ENABLED(OF_PLATDATA)
             /* Decode the of-platdata from the C structures */
@@ -294,12 +294,12 @@ For example:
             .of_to_plat = mmc_of_to_plat,
             .probe          = mmc_probe,
             .priv_auto = sizeof(struct mmc_priv),
-            .plat_auto = sizeof(struct mmc_platdata),
+            .plat_auto = sizeof(struct mmc_plat),
     };
 
     U_BOOT_DRIVER_ALIAS(mmc_drv, vendor_mmc) /* matches compatible string */
 
-Note that struct mmc_platdata is defined in the C file, not in a header. This
+Note that struct mmc_plat is defined in the C file, not in a header. This
 is to avoid needing to include dt-structs.h in a header file. The idea is to
 keep the use of each of-platdata struct to the smallest possible code area.
 There is just one driver C file for each struct, that can convert from the

doc/driver-model/spi-howto.rst

@@ -209,7 +209,7 @@ DM tells you. The name is not quite right. So in this case we would use:
 
 .. code-block:: c
 
-	struct exynos_spi_platdata {
+	struct exynos_spi_plat {
 		enum periph_id periph_id;
 		s32 frequency;		/* Default clock frequency, -1 for none */
 		struct exynos_spi *regs;
@@ -231,7 +231,7 @@ tree, but we need to tell it the size:
 
 	U_BOOT_DRIVER(spi_exynos) = {
 	...
-		.plat_auto = sizeof(struct exynos_spi_platdata),
+		.plat_auto = sizeof(struct exynos_spi_plat),
 
 
 Here is a sample function. It gets a pointer to the platform data and
@@ -241,7 +241,7 @@ fills in the fields from device tree.
 
 	static int exynos_spi_of_to_plat(struct udevice *bus)
 	{
-		struct exynos_spi_platdata *plat = bus->plat;
+		struct exynos_spi_plat *plat = bus->plat;
 		const void *blob = gd->fdt_blob;
 		int node = dev_of_offset(bus);
 
@@ -274,7 +274,7 @@ Specify this data in a U_BOOT_DEVICE() declaration in your board file:
 
 .. code-block:: c
 
-	struct exynos_spi_platdata platdata_spi0 = {
+	struct exynos_spi_plat platdata_spi0 = {
 		.periph_id = ...
 		.frequency = ...
 		.regs = ...
@@ -357,7 +357,7 @@ what you can copy out to set things up.
 
 	static int exynos_spi_probe(struct udevice *bus)
 	{
-		struct exynos_spi_platdata *plat = dev_get_plat(bus);
+		struct exynos_spi_plat *plat = dev_get_plat(bus);
 		struct exynos_spi_priv *priv = dev_get_priv(bus);
 
 		priv->regs = plat->regs;
@@ -437,7 +437,7 @@ Here is an example for the speed part:
 
 	static int exynos_spi_set_speed(struct udevice *bus, uint speed)
 	{
-		struct exynos_spi_platdata *plat = bus->plat;
+		struct exynos_spi_plat *plat = bus->plat;
 		struct exynos_spi_priv *priv = dev_get_priv(bus);
 		int ret;
 
@@ -585,7 +585,7 @@ The new version looks like this:
 	static void spi_cs_activate(struct udevice *dev)
 	{
 		struct udevice *bus = dev->parent;
-		struct exynos_spi_platdata *pdata = dev_get_plat(bus);
+		struct exynos_spi_plat *pdata = dev_get_plat(bus);
 		struct exynos_spi_priv *priv = dev_get_priv(bus);
 
 		/* If it's too soon to do another transaction, wait */
@@ -657,7 +657,7 @@ A little note about SPI uclass features
 
 The SPI uclass keeps some information about each device 'dev' on the bus:
 
-   struct dm_spi_slave_platdata:
+   struct dm_spi_slave_plat:
      This is device_get_parent_plat(dev).
      This is where the chip select number is stored, along with
      the default bus speed and mode. It is automatically read

doc/driver-model/usb-info.rst

@@ -43,7 +43,7 @@ as drivers in the USB uclass. For example:
 		.probe = tegra_ehci_usb_probe,
 		.remove = tegra_ehci_usb_remove,
 		.ops	= &ehci_usb_ops,
-		.plat_auto = sizeof(struct usb_platdata),
+		.plat_auto = sizeof(struct usb_plat),
 		.priv_auto = sizeof(struct fdt_usb),
 		.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 	};
@@ -63,7 +63,7 @@ This can hold run-time information needed by the driver for operation. It
 exists when the device is probed (not when it is bound) and is removed when
 the driver is removed.
 
-Note that usb_platdata is currently only used to deal with setting up a bus
+Note that usb_plat is currently only used to deal with setting up a bus
 in USB device mode (OTG operation). It can be omitted if that is not
 supported.
 
@@ -93,12 +93,12 @@ The following primary data structures are in use:
 	handles that). Once the device is set up, you can find the device
 	descriptor and current configuration descriptor in this structure.
 
-- struct usb_platdata:
+- struct usb_plat:
 	This holds platform data for a controller. So far this is only used
 	as a work-around for controllers which can act as USB devices in OTG
 	mode, since the gadget framework does not use driver model.
 
-- struct usb_dev_platdata:
+- struct usb_dev_plat:
 	This holds platform data for a device. You can access it for a
 	device 'dev' with dev_get_parent_plat(dev). It holds the device
 	address and speed - anything that can be determined before the device

drivers/adc/adc-uclass.c

@@ -267,7 +267,7 @@ try_manual:
 	return _adc_channels_single_shot(dev, channel_mask, channels);
 }
 
-static int adc_vdd_platdata_update(struct udevice *dev)
+static int adc_vdd_plat_update(struct udevice *dev)
 {
 	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
 	int ret;
@@ -290,7 +290,7 @@ static int adc_vdd_platdata_update(struct udevice *dev)
 	return 0;
 }
 
-static int adc_vss_platdata_update(struct udevice *dev)
+static int adc_vss_plat_update(struct udevice *dev)
 {
 	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
 	int ret;
@@ -313,7 +313,7 @@ int adc_vdd_value(struct udevice *dev, int *uV)
 	int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1;
 
 	/* Update the regulator Value. */
-	ret = adc_vdd_platdata_update(dev);
+	ret = adc_vdd_plat_update(dev);
 	if (ret)
 		return ret;
 
@@ -331,7 +331,7 @@ int adc_vss_value(struct udevice *dev, int *uV)
 	int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1;
 
 	/* Update the regulator Value. */
-	ret = adc_vss_platdata_update(dev);
+	ret = adc_vss_plat_update(dev);
 	if (ret)
 		return ret;
 
@@ -367,7 +367,7 @@ int adc_raw_to_uV(struct udevice *dev, unsigned int raw, int *uV)
 	return 0;
 }
 
-static int adc_vdd_platdata_set(struct udevice *dev)
+static int adc_vdd_plat_set(struct udevice *dev)
 {
 	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
 	int ret;
@@ -380,7 +380,7 @@ static int adc_vdd_platdata_set(struct udevice *dev)
 	ret = device_get_supply_regulator(dev, "vdd-supply",
 					  &uc_pdata->vdd_supply);
 	if (!ret)
-		return adc_vdd_platdata_update(dev);
+		return adc_vdd_plat_update(dev);
 
 	if (ret != -ENOENT)
 		return ret;
@@ -392,7 +392,7 @@ static int adc_vdd_platdata_set(struct udevice *dev)
 	return 0;
 }
 
-static int adc_vss_platdata_set(struct udevice *dev)
+static int adc_vss_plat_set(struct udevice *dev)
 {
 	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
 	int ret;
@@ -404,7 +404,7 @@ static int adc_vss_platdata_set(struct udevice *dev)
 	ret = device_get_supply_regulator(dev, "vss-supply",
 					  &uc_pdata->vss_supply);
 	if (!ret)
-		return adc_vss_platdata_update(dev);
+		return adc_vss_plat_update(dev);
 
 	if (ret != -ENOENT)
 		return ret;
@@ -421,12 +421,12 @@ static int adc_pre_probe(struct udevice *dev)
 	int ret;
 
 	/* Set ADC VDD plat: polarity, uV, regulator (phandle). */
-	ret = adc_vdd_platdata_set(dev);
+	ret = adc_vdd_plat_set(dev);
 	if (ret)
 		pr_err("%s: Can't update Vdd. Error: %d", dev->name, ret);
 
 	/* Set ADC VSS plat: polarity, uV, regulator (phandle). */
-	ret = adc_vss_platdata_set(dev);
+	ret = adc_vss_plat_set(dev);
 	if (ret)
 		pr_err("%s: Can't update Vss. Error: %d", dev->name, ret);
 

drivers/ata/ahci.c

@@ -172,7 +172,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
 # ifdef CONFIG_DM_PCI
 	struct udevice *dev = uc_priv->dev;
-	struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+	struct pci_child_plat *pplat = dev_get_parent_plat(dev);
 # else
 	pci_dev_t pdev = uc_priv->dev;
 	unsigned short vendor;
@@ -474,7 +474,7 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
 		pci_write_config_byte(dev, 0x41, 0xa1);
 #endif
 #else
-	struct scsi_platdata *plat = dev_get_uclass_plat(dev);
+	struct scsi_plat *plat = dev_get_uclass_plat(dev);
 	uc_priv->mmio_base = (void *)plat->base;
 #endif
 
@@ -1163,7 +1163,7 @@ int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
 {
 	struct ahci_uc_priv *uc_priv;
-	struct scsi_platdata *uc_plat;
+	struct scsi_plat *uc_plat;
 	struct udevice *dev;
 	int ret;
 

drivers/clk/altera/clk-agilex.c

@@ -17,7 +17,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct socfpga_clk_platdata {
+struct socfpga_clk_plat {
 	void __iomem *regs;
 };
 
@@ -25,20 +25,20 @@ struct socfpga_clk_platdata {
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
-static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
 {
 	CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
 	cm_wait_for_fsm();
 }
 
-static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
 {
 	CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
 	cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
-static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
 {
 	CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
 	cm_wait_for_fsm();
@@ -108,7 +108,7 @@ static const struct {
 	},
 };
 
-static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll,
 			       int timeout)
 {
 	int cnt = 0;
@@ -133,7 +133,7 @@ static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
 	return 0;
 }
 
-static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll,
 			    u32 addr_offset, u32 wdat, int timeout)
 {
 	u32 addr;
@@ -154,7 +154,7 @@ static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
 	return membus_wait_for_req(plat, pll, timeout);
 }
 
-static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll,
 			   u32 addr_offset, u32 *rdata, int timeout)
 {
 	u32 addr;
@@ -184,7 +184,7 @@ static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
 	return 0;
 }
 
-static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
+static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll)
 {
 	int i;
 	u32 rdata;
@@ -236,7 +236,7 @@ static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
 static void clk_basic_init(struct udevice *dev,
 			   const struct cm_config * const cfg)
 {
-	struct socfpga_clk_platdata *plat = dev_get_plat(dev);
+	struct socfpga_clk_plat *plat = dev_get_plat(dev);
 	u32 vcocalib;
 
 	if (!cfg)
@@ -342,7 +342,7 @@ static void clk_basic_init(struct udevice *dev,
 		       CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
 }
 
-static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
 			      u32 pllglob_reg, u32 pllm_reg)
 {
 	 u64 fref, arefdiv, mdiv, reg, vco;
@@ -375,26 +375,26 @@ static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
 	return vco;
 }
 
-static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
 {
 	return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
 				 CLKMGR_MAINPLL_PLLM);
 }
 
-static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
 {
 	return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
 				 CLKMGR_PERPLL_PLLM);
 }
 
-static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
 {
 	u32 clksrc = CM_REG_READL(plat, reg);
 
 	return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
 }
 
-static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
 			     u32 main_reg, u32 per_reg)
 {
 	u64 clock;
@@ -431,7 +431,7 @@ static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
 	return clock;
 }
 
-static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
 {
 	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
 				      CLKMGR_MAINPLL_PLLC0,
@@ -443,14 +443,14 @@ static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
 	return clock;
 }
 
-static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
 {
 	return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
 				      CLKMGR_MAINPLL_PLLC1,
 				      CLKMGR_PERPLL_PLLC1);
 }
 
-static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
 {
 	u64 clock = clk_get_l3_main_clk_hz(plat);
 
@@ -461,7 +461,7 @@ static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
 	return clock;
 }
 
-static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
 {
 	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
 				      CLKMGR_MAINPLL_PLLC3,
@@ -473,7 +473,7 @@ static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
 	return clock / 4;
 }
 
-static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
 {
 	u64 clock = clk_get_l3_main_clk_hz(plat);
 
@@ -484,7 +484,7 @@ static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
 	return clock;
 }
 
-static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
 {
 	u64 clock = clk_get_l3_main_clk_hz(plat);
 
@@ -495,7 +495,7 @@ static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
 	return clock;
 }
 
-static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
 {
 	if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
 		return clk_get_l3_main_clk_hz(plat) / 2;
@@ -503,7 +503,7 @@ static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
 	return clk_get_l3_main_clk_hz(plat) / 4;
 }
 
-static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
 {
 	bool emacsel_a;
 	u32 ctl;
@@ -585,7 +585,7 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
 
 static ulong socfpga_clk_get_rate(struct clk *clk)
 {
-	struct socfpga_clk_platdata *plat = dev_get_plat(clk->dev);
+	struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
 
 	switch (clk->id) {
 	case AGILEX_MPU_CLK:
@@ -630,7 +630,7 @@ static int socfpga_clk_probe(struct udevice *dev)
 
 static int socfpga_clk_of_to_plat(struct udevice *dev)
 {
-	struct socfpga_clk_platdata *plat = dev_get_plat(dev);
+	struct socfpga_clk_plat *plat = dev_get_plat(dev);
 	fdt_addr_t addr;
 
 	addr = dev_read_addr(dev);
@@ -658,5 +658,5 @@ U_BOOT_DRIVER(socfpga_agilex_clk) = {
 	.ops		= &socfpga_clk_ops,
 	.probe		= socfpga_clk_probe,
 	.of_to_plat = socfpga_clk_of_to_plat,
-	.plat_auto	= sizeof(struct socfpga_clk_platdata),
+	.plat_auto	= sizeof(struct socfpga_clk_plat),
 };

drivers/clk/altera/clk-arria10.c

@@ -24,7 +24,7 @@ enum socfpga_a10_clk_type {
 	SOCFPGA_A10_CLK_UNKNOWN_CLK,
 };
 
-struct socfpga_a10_clk_platdata {
+struct socfpga_a10_clk_plat {
 	enum socfpga_a10_clk_type type;
 	struct clk_bulk	clks;
 	u32		regs;
@@ -43,7 +43,7 @@ struct socfpga_a10_clk_platdata {
 
 static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
 	u32 reg, maxval;
 
 	if (plat->clks.count == 0)
@@ -84,7 +84,7 @@ static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
 
 static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
 	struct clk *upclk = NULL;
 	int ret;
 
@@ -120,7 +120,7 @@ static int socfpga_a10_clk_disable(struct clk *clk)
 
 static ulong socfpga_a10_clk_get_rate(struct clk *clk)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
 	struct clk *upclk = NULL;
 	ulong rate = 0, reg, numer, denom;
 	int ret;
@@ -190,7 +190,7 @@ static struct clk_ops socfpga_a10_clk_ops = {
  */
 static void socfpga_a10_handoff_workaround(struct udevice *dev)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
 	const void *fdt = gd->fdt_blob;
 	struct clk_bulk	*bulk = &plat->clks;
 	int i, ret, offset = dev_of_offset(dev);
@@ -274,8 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
 
 static int socfpga_a10_clk_probe(struct udevice *dev)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
-	struct socfpga_a10_clk_platdata *pplat;
+	struct socfpga_a10_clk_plat *pplat;
 	struct udevice *pdev;
 	const void *fdt = gd->fdt_blob;
 	int offset = dev_of_offset(dev);
@@ -321,7 +321,7 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
 
 static int socfpga_a10_of_to_plat(struct udevice *dev)
 {
-	struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
+	struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
 	unsigned int divreg[3], gatereg[2];
 	int ret;
 
@@ -359,5 +359,5 @@ U_BOOT_DRIVER(socfpga_a10_clk) = {
 	.probe		= socfpga_a10_clk_probe,
 	.of_to_plat = socfpga_a10_of_to_plat,
 
-	.plat_auto	= sizeof(struct socfpga_a10_clk_platdata),
+	.plat_auto	= sizeof(struct socfpga_a10_clk_plat),
 };

drivers/clk/at91/compat.c

@@ -21,7 +21,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct pmc_platdata {
+struct pmc_plat {
 	struct at91_pmc *reg_base;
 	struct regmap *regmap_sfr;
 };
@@ -45,7 +45,7 @@ U_BOOT_DRIVER(at91_pmc) = {
 
 static int at91_pmc_core_probe(struct udevice *dev)
 {
-	struct pmc_platdata *plat = dev_get_plat(dev);
+	struct pmc_plat *plat = dev_get_plat(dev);
 
 	dev = dev_get_parent(dev);
 
@@ -115,7 +115,7 @@ int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 int at91_clk_probe(struct udevice *dev)
 {
 	struct udevice *dev_periph_container, *dev_pmc;
-	struct pmc_platdata *plat = dev_get_plat(dev);
+	struct pmc_plat *plat = dev_get_plat(dev);
 
 	dev_periph_container = dev_get_parent(dev);
 	dev_pmc = dev_get_parent(dev_periph_container);
@@ -191,7 +191,7 @@ U_BOOT_DRIVER(at91_master_clk) = {
 /* Main osc clock specific code. */
 static int main_osc_clk_enable(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 
 	if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
@@ -225,14 +225,14 @@ U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = main_osc_clk_match,
 	.probe = main_osc_clk_probe,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &main_osc_clk_ops,
 };
 
 /* PLLA clock specific code. */
 static int plla_clk_enable(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 
 	if (readl(&pmc->sr) & AT91_PMC_LOCKA)
@@ -266,7 +266,7 @@ U_BOOT_DRIVER(at91_plla_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = plla_clk_match,
 	.probe = plla_clk_probe,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &plla_clk_ops,
 };
 
@@ -278,7 +278,7 @@ static int at91_plladiv_clk_enable(struct clk *clk)
 
 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct clk source;
 	ulong clk_rate;
@@ -297,7 +297,7 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk)
 
 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct clk source;
 	ulong parent_rate;
@@ -340,7 +340,7 @@ U_BOOT_DRIVER(at91_plladiv_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = at91_plladiv_clk_match,
 	.probe = at91_plladiv_clk_probe,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &at91_plladiv_clk_ops,
 };
 
@@ -401,7 +401,7 @@ static ulong system_clk_set_rate(struct clk *clk, ulong rate)
 
 static int system_clk_enable(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	u32 mask;
 
@@ -437,7 +437,7 @@ U_BOOT_DRIVER(system_clk) = {
 	.name = "system-clk",
 	.id = UCLASS_CLK,
 	.probe = at91_clk_probe,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &system_clk_ops,
 };
 
@@ -483,7 +483,7 @@ U_BOOT_DRIVER(sam9x5_periph_clk) = {
 
 static int periph_clk_enable(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	enum periph_clk_type clk_type;
 	void *addr;
@@ -536,7 +536,7 @@ static struct clk_ops periph_clk_ops = {
 U_BOOT_DRIVER(clk_periph) = {
 	.name	= "periph-clk",
 	.id	= UCLASS_CLK,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.probe = at91_clk_probe,
 	.ops	= &periph_clk_ops,
 };
@@ -552,7 +552,7 @@ U_BOOT_DRIVER(clk_periph) = {
 
 static int utmi_clk_enable(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct clk clk_dev;
 	ulong clk_rate;
@@ -640,7 +640,7 @@ static struct clk_ops utmi_clk_ops = {
 
 static int utmi_clk_of_to_plat(struct udevice *dev)
 {
-	struct pmc_platdata *plat = dev_get_plat(dev);
+	struct pmc_plat *plat = dev_get_plat(dev);
 	struct udevice *syscon;
 
 	uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
@@ -668,7 +668,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
 	.of_match = utmi_clk_match,
 	.probe = utmi_clk_probe,
 	.of_to_plat = utmi_clk_of_to_plat,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &utmi_clk_ops,
 };
 
@@ -681,7 +681,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
 
 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	ulong rate = gd->arch.mck_rate_hz;
 
@@ -713,7 +713,7 @@ U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = sama5d4_h32mx_clk_match,
 	.probe = sama5d4_h32mx_clk_probe,
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &sama5d4_h32mx_clk_ops,
 };
 
@@ -754,7 +754,7 @@ struct generic_clk_priv {
 
 static ulong generic_clk_get_rate(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct clk parent;
 	ulong clk_rate;
@@ -782,7 +782,7 @@ static ulong generic_clk_get_rate(struct clk *clk)
 
 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct generic_clk_priv *priv = dev_get_priv(clk->dev);
 	struct clk parent, best_parent;
@@ -877,7 +877,7 @@ U_BOOT_DRIVER(generic_clk) = {
 	.probe = at91_clk_probe,
 	.of_to_plat = generic_clk_of_to_plat,
 	.priv_auto	= sizeof(struct generic_clk_priv),
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &generic_clk_ops,
 };
 
@@ -895,7 +895,7 @@ struct at91_usb_clk_priv {
 
 static ulong at91_usb_clk_get_rate(struct clk *clk)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct clk source;
 	u32 tmp, usbdiv;
@@ -916,7 +916,7 @@ static ulong at91_usb_clk_get_rate(struct clk *clk)
 
 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct pmc_platdata *plat = dev_get_plat(clk->dev);
+	struct pmc_plat *plat = dev_get_plat(clk->dev);
 	struct at91_pmc *pmc = plat->reg_base;
 	struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
 	struct clk source, best_source;
@@ -1013,7 +1013,7 @@ U_BOOT_DRIVER(at91_usb_clk) = {
 	.probe = at91_usb_clk_probe,
 	.of_to_plat = at91_usb_clk_of_to_plat,
 	.priv_auto	= sizeof(struct at91_usb_clk_priv),
-	.plat_auto	= sizeof(struct pmc_platdata),
+	.plat_auto	= sizeof(struct pmc_plat),
 	.ops = &at91_usb_clk_ops,
 };
 

drivers/core/regmap.c

@@ -60,8 +60,8 @@ static struct regmap *regmap_alloc(int count)
 }
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
+int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
-			     struct regmap **mapp)
+			 struct regmap **mapp)
 {
 	struct regmap_range *range;
 	struct regmap *map;

drivers/core/root.c

@@ -174,7 +174,7 @@ int dm_remove_devices_flags(uint flags)
 }
 #endif
 
-int dm_scan_platdata(bool pre_reloc_only)
+int dm_scan_plat(bool pre_reloc_only)
 {
 	int ret;
 
@@ -308,9 +308,9 @@ int dm_init_and_scan(bool pre_reloc_only)
 		debug("dm_init() failed: %d\n", ret);
 		return ret;
 	}
-	ret = dm_scan_platdata(pre_reloc_only);
+	ret = dm_scan_plat(pre_reloc_only);
 	if (ret) {
-		debug("dm_scan_platdata() failed: %d\n", ret);
+		debug("dm_scan_plat() failed: %d\n", ret);
 		return ret;
 	}
 

drivers/core/syscon-uclass.c

@@ -56,9 +56,9 @@ static int syscon_pre_probe(struct udevice *dev)
 	 * using OF_PLATDATA will need to ensure that this is true.
 	 */
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct syscon_base_platdata *plat = dev_get_plat(dev);
+	struct syscon_base_plat *plat = dev_get_plat(dev);
 
-	return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg),
+	return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
 					&priv->regmap);
 #else
 	return regmap_init_mem(dev_ofnode(dev), &priv->regmap);

drivers/cpu/at91_cpu.c

@@ -11,7 +11,7 @@
 #include <div64.h>
 #include <linux/clk-provider.h>
 
-struct at91_cpu_platdata {
+struct at91_cpu_plat {
 	const char *name;
 	ulong cpufreq_mhz;
 	ulong mckfreq_mhz;
@@ -27,7 +27,7 @@ const char *at91_cpu_get_name(void)
 
 int at91_cpu_get_desc(const struct udevice *dev, char *buf, int size)
 {
-	struct at91_cpu_platdata *plat = dev_get_plat(dev);
+	struct at91_cpu_plat *plat = dev_get_plat(dev);
 
 	snprintf(buf, size, "%s\n"
 		 "Crystal frequency: %8lu MHz\n"
@@ -41,7 +41,7 @@ int at91_cpu_get_desc(const struct udevice *dev, char *buf, int size)
 
 static int at91_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
 {
-	struct at91_cpu_platdata *plat = dev_get_plat(dev);
+	struct at91_cpu_plat *plat = dev_get_plat(dev);
 
 	info->cpu_freq = plat->cpufreq_mhz * 1000000;
 	info->features = BIT(CPU_FEAT_L1_CACHE);
@@ -75,7 +75,7 @@ static const struct udevice_id at91_cpu_ids[] = {
 
 static int at91_cpu_probe(struct udevice *dev)
 {
-	struct at91_cpu_platdata *plat = dev_get_plat(dev);
+	struct at91_cpu_plat *plat = dev_get_plat(dev);
 	struct clk clk;
 	ulong rate;
 	int ret;
@@ -118,6 +118,6 @@ U_BOOT_DRIVER(cpu_at91_drv) = {
 	.of_match	= at91_cpu_ids,
 	.ops		= &at91_cpu_ops,
 	.probe		= at91_cpu_probe,
-	.plat_auto	= sizeof(struct at91_cpu_platdata),
+	.plat_auto	= sizeof(struct at91_cpu_plat),
 	.flags		= DM_FLAG_PRE_RELOC,
 };

drivers/cpu/bmips_cpu.c

@@ -425,7 +425,7 @@ static const struct cpu_ops bmips_cpu_ops = {
 /* BMIPS CPU driver */
 int bmips_cpu_bind(struct udevice *dev)
 {
-	struct cpu_platdata *plat = dev_get_parent_plat(dev);
+	struct cpu_plat *plat = dev_get_parent_plat(dev);
 
 	plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
 	plat->device_id = read_c0_prid();

drivers/cpu/cpu-uclass.c

@@ -115,7 +115,7 @@ int cpu_get_vendor(const struct udevice *dev, char *buf, int size)
 U_BOOT_DRIVER(cpu_bus) = {
 	.name	= "cpu_bus",
 	.id	= UCLASS_SIMPLE_BUS,
-	.per_child_plat_auto	= sizeof(struct cpu_platdata),
+	.per_child_plat_auto	= sizeof(struct cpu_plat),
 };
 
 static int uclass_cpu_init(struct uclass *uc)

drivers/cpu/cpu_sandbox.c

@@ -64,7 +64,7 @@ static const struct cpu_ops cpu_sandbox_ops = {
 static int cpu_sandbox_bind(struct udevice *dev)
 {
 	int ret;
-	struct cpu_platdata *plat = dev_get_parent_plat(dev);
+	struct cpu_plat *plat = dev_get_parent_plat(dev);
 
 	/* first examine the property in current cpu node */
 	ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);

drivers/cpu/imx8_cpu.c

@@ -16,7 +16,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct cpu_imx_platdata {
+struct cpu_imx_plat {
 	const char *name;
 	const char *rev;
 	const char *type;
@@ -55,7 +55,7 @@ const char *get_imx8_rev(u32 rev)
 
 static void set_core_data(struct udevice *dev)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 
 	if (device_is_compatible(dev, "arm,cortex-a35")) {
 		plat->cpu_rsrc = SC_R_A35;
@@ -73,7 +73,7 @@ static void set_core_data(struct udevice *dev)
 }
 
 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
 {
 	struct udevice *thermal_dev;
 	int cpu_tmp, ret;
@@ -94,7 +94,7 @@ static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
 	return cpu_tmp;
 }
 #else
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
 {
 	return 0;
 }
@@ -102,7 +102,7 @@ static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
 
 int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 	int ret, temp;
 
 	if (size < 100)
@@ -128,7 +128,7 @@ int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 
 static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 
 	info->cpu_freq = plat->freq_mhz * 1000;
 	info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
@@ -165,7 +165,7 @@ static int cpu_imx_get_vendor(const struct udevice *dev,  char *buf, int size)
 
 static int cpu_imx_is_current(struct udevice *dev)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 
 	if (plat->mpidr == (read_mpidr() & 0xffff))
 		return 1;
@@ -190,7 +190,7 @@ static const struct udevice_id cpu_imx8_ids[] = {
 
 static ulong imx8_get_cpu_rate(struct udevice *dev)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 	ulong rate;
 	int ret;
 
@@ -206,7 +206,7 @@ static ulong imx8_get_cpu_rate(struct udevice *dev)
 
 static int imx8_cpu_probe(struct udevice *dev)
 {
-	struct cpu_imx_platdata *plat = dev_get_plat(dev);
+	struct cpu_imx_plat *plat = dev_get_plat(dev);
 	u32 cpurev;
 
 	set_core_data(dev);
@@ -230,6 +230,6 @@ U_BOOT_DRIVER(cpu_imx8_drv) = {
 	.of_match	= cpu_imx8_ids,
 	.ops		= &cpu_imx8_ops,
 	.probe		= imx8_cpu_probe,
-	.plat_auto	= sizeof(struct cpu_imx_platdata),
+	.plat_auto	= sizeof(struct cpu_imx_plat),
 	.flags		= DM_FLAG_PRE_RELOC,
 };

drivers/cpu/riscv_cpu.c

@@ -91,7 +91,7 @@ static int riscv_cpu_get_count(const struct udevice *dev)
 
 static int riscv_cpu_bind(struct udevice *dev)
 {
-	struct cpu_platdata *plat = dev_get_parent_plat(dev);
+	struct cpu_plat *plat = dev_get_parent_plat(dev);
 	struct driver *drv;
 	int ret;
 

drivers/ddr/altera/sdram_agilex.c

@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int sdram_mmr_init_full(struct udevice *dev)
 {
-	struct altera_sdram_platdata *plat = dev->plat;
+	struct altera_sdram_plat *plat = dev->plat;
 	struct altera_sdram_priv *priv = dev_get_priv(dev);
 	u32 i;
 	int ret;

drivers/ddr/altera/sdram_gen5.c

@@ -27,7 +27,7 @@ struct altera_gen5_sdram_priv {
 	struct ram_info info;
 };
 
-struct altera_gen5_sdram_platdata {
+struct altera_gen5_sdram_plat {
 	struct socfpga_sdr *sdr;
 };
 
@@ -565,7 +565,7 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 
 static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
 {
-	struct altera_gen5_sdram_platdata *plat = dev->plat;
+	struct altera_gen5_sdram_plat *plat = dev->plat;
 
 	plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
 	if (!plat->sdr)
@@ -578,7 +578,7 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
 {
 	int ret;
 	unsigned long sdram_size;
-	struct altera_gen5_sdram_platdata *plat = dev->plat;
+	struct altera_gen5_sdram_plat *plat = dev->plat;
 	struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
 	struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
 	struct reset_ctl_bulk resets;
@@ -647,7 +647,7 @@ U_BOOT_DRIVER(altera_gen5_sdram) = {
 	.of_match = altera_gen5_sdram_ids,
 	.ops = &altera_gen5_sdram_ops,
 	.of_to_plat = altera_gen5_sdram_of_to_plat,
-	.plat_auto	= sizeof(struct altera_gen5_sdram_platdata),
+	.plat_auto	= sizeof(struct altera_gen5_sdram_plat),
 	.probe = altera_gen5_sdram_probe,
 	.priv_auto	= sizeof(struct altera_gen5_sdram_priv),
 };

drivers/ddr/altera/sdram_s10.c

@@ -70,7 +70,7 @@ int match_ddr_conf(u32 ddr_conf)
  */
 int sdram_mmr_init_full(struct udevice *dev)
 {
-	struct altera_sdram_platdata *plat = dev->plat;
+	struct altera_sdram_plat *plat = dev->plat;
 	struct altera_sdram_priv *priv = dev_get_priv(dev);
 	u32 update_value, io48_value, ddrioctl;
 	u32 i;

drivers/ddr/altera/sdram_soc64.c

@@ -27,29 +27,29 @@
 
 #define PGTABLE_OFF	0x4000
 
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
 	return readl(plat->iomhc + reg);
 }
 
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
 	return readl(plat->hmc + reg);
 }
 
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
 		   u32 data, u32 reg)
 {
 	return writel(data, plat->hmc + reg);
 }
 
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
 		   u32 reg)
 {
 	return writel(data, plat->ddr_sch + reg);
 }
 
-int emif_clear(struct altera_sdram_platdata *plat)
+int emif_clear(struct altera_sdram_plat *plat)
 {
 	hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
 
@@ -59,7 +59,7 @@ int emif_clear(struct altera_sdram_platdata *plat)
 				 false, 1000, false);
 }
 
-int emif_reset(struct altera_sdram_platdata *plat)
+int emif_reset(struct altera_sdram_plat *plat)
 {
 	u32 c2s, s2c, ret;
 
@@ -214,7 +214,7 @@ void sdram_size_check(struct bd_info *bd)
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
 {
 	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 
@@ -232,7 +232,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
 
 static int altera_sdram_of_to_plat(struct udevice *dev)
 {
-	struct altera_sdram_platdata *plat = dev->plat;
+	struct altera_sdram_plat *plat = dev->plat;
 	fdt_addr_t addr;
 
 	addr = dev_read_addr_index(dev, 0);
@@ -304,7 +304,7 @@ U_BOOT_DRIVER(altera_sdram) = {
 	.of_match = altera_sdram_ids,
 	.ops = &altera_sdram_ops,
 	.of_to_plat = altera_sdram_of_to_plat,
-	.plat_auto	= sizeof(struct altera_sdram_platdata),
+	.plat_auto	= sizeof(struct altera_sdram_plat),
 	.probe = altera_sdram_probe,
 	.priv_auto	= sizeof(struct altera_sdram_priv),
 };

drivers/ddr/altera/sdram_soc64.h

@@ -14,7 +14,7 @@ struct altera_sdram_priv {
 	struct reset_ctl_bulk resets;
 };
 
-struct altera_sdram_platdata {
+struct altera_sdram_plat {
 	void __iomem *hmc;
 	void __iomem *ddr_sch;
 	void __iomem *iomhc;
@@ -169,19 +169,19 @@ struct altera_sdram_platdata {
 #define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
 #define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
 
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg);
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg);
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
 		   u32 data, u32 reg);
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
 		   u32 reg);
-int emif_clear(struct altera_sdram_platdata *plat);
+int emif_clear(struct altera_sdram_plat *plat);
-int emif_reset(struct altera_sdram_platdata *plat);
+int emif_reset(struct altera_sdram_plat *plat);
 int poll_hmc_clock_status(void);
 void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
 void sdram_init_ecc_bits(struct bd_info *bd);
 void sdram_size_check(struct bd_info *bd);
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
 int sdram_mmr_init_full(struct udevice *dev);
 
 #endif /* _SDRAM_SOC64_H_ */

drivers/gpio/altera_pio.c

@@ -19,7 +19,7 @@ struct altera_pio_regs {
 	u32	direction;		/* Direction register */
 };
 
-struct altera_pio_platdata {
+struct altera_pio_plat {
 	struct altera_pio_regs *regs;
 	int gpio_count;
 	const char *bank_name;
@@ -27,7 +27,7 @@ struct altera_pio_platdata {
 
 static int altera_pio_direction_input(struct udevice *dev, unsigned pin)
 {
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 	struct altera_pio_regs *const regs = plat->regs;
 
 	clrbits_le32(&regs->direction, 1 << pin);
@@ -38,7 +38,7 @@ static int altera_pio_direction_input(struct udevice *dev, unsigned pin)
 static int altera_pio_direction_output(struct udevice *dev, unsigned pin,
 				     int val)
 {
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 	struct altera_pio_regs *const regs = plat->regs;
 
 	if (val)
@@ -53,7 +53,7 @@ static int altera_pio_direction_output(struct udevice *dev, unsigned pin,
 
 static int altera_pio_get_value(struct udevice *dev, unsigned pin)
 {
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 	struct altera_pio_regs *const regs = plat->regs;
 
 	return !!(readl(&regs->data) & (1 << pin));
@@ -62,7 +62,7 @@ static int altera_pio_get_value(struct udevice *dev, unsigned pin)
 
 static int altera_pio_set_value(struct udevice *dev, unsigned pin, int val)
 {
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 	struct altera_pio_regs *const regs = plat->regs;
 
 	if (val)
@@ -76,7 +76,7 @@ static int altera_pio_set_value(struct udevice *dev, unsigned pin, int val)
 static int altera_pio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 
 	uc_priv->gpio_count = plat->gpio_count;
 	uc_priv->bank_name = plat->bank_name;
@@ -86,7 +86,7 @@ static int altera_pio_probe(struct udevice *dev)
 
 static int altera_pio_of_to_plat(struct udevice *dev)
 {
-	struct altera_pio_platdata *plat = dev_get_plat(dev);
+	struct altera_pio_plat *plat = dev_get_plat(dev);
 
 	plat->regs = map_physmem(dev_read_addr(dev),
 				 sizeof(struct altera_pio_regs),
@@ -117,6 +117,6 @@ U_BOOT_DRIVER(altera_pio) = {
 	.of_match	= altera_pio_ids,
 	.ops		= &altera_pio_ops,
 	.of_to_plat = altera_pio_of_to_plat,
-	.plat_auto	= sizeof(struct altera_pio_platdata),
+	.plat_auto	= sizeof(struct altera_pio_plat),
 	.probe		= altera_pio_probe,
 };

drivers/gpio/at91_gpio.c

@@ -590,7 +590,7 @@ static const struct dm_gpio_ops gpio_at91_ops = {
 static int at91_gpio_probe(struct udevice *dev)
 {
 	struct at91_port_priv *port = dev_get_priv(dev);
-	struct at91_port_platdata *plat = dev_get_plat(dev);
+	struct at91_port_plat *plat = dev_get_plat(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct clk clk;
 	int ret;
@@ -629,7 +629,7 @@ U_BOOT_DRIVER(atmel_at91rm9200_gpio) = {
 	.id	= UCLASS_GPIO,
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 	.of_match = at91_gpio_ids,
-	.plat_auto	= sizeof(struct at91_port_platdata),
+	.plat_auto	= sizeof(struct at91_port_plat),
 #endif
 	.ops	= &gpio_at91_ops,
 	.probe	= at91_gpio_probe,

drivers/gpio/atmel_pio4.c

@@ -176,14 +176,14 @@ struct atmel_pioctrl_data {
 	u32 nbanks;
 };
 
-struct atmel_pio4_platdata {
+struct atmel_pio4_plat {
 	struct atmel_pio4_port *reg_base;
 };
 
 static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
 						    u32 bank)
 {
-	struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+	struct atmel_pio4_plat *plat = dev_get_plat(dev);
 	struct atmel_pio4_port *port_base =
 			(struct atmel_pio4_port *)((u32)plat->reg_base +
 			ATMEL_PIO_BANK_OFFSET * bank);
@@ -281,7 +281,7 @@ static int atmel_pio4_bind(struct udevice *dev)
 
 static int atmel_pio4_probe(struct udevice *dev)
 {
-	struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+	struct atmel_pio4_plat *plat = dev_get_plat(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct atmel_pioctrl_data *pioctrl_data;
 	struct clk clk;
@@ -338,7 +338,7 @@ U_BOOT_DRIVER(gpio_atmel_pio4) = {
 	.probe	= atmel_pio4_probe,
 	.bind	= atmel_pio4_bind,
 	.of_match = atmel_pio4_ids,
-	.plat_auto	= sizeof(struct atmel_pio4_platdata),
+	.plat_auto	= sizeof(struct atmel_pio4_plat),
 };
 
 #endif

drivers/gpio/bcm2835_gpio.c

@@ -102,7 +102,7 @@ static const struct dm_gpio_ops gpio_bcm2835_ops = {
 static int bcm2835_gpio_probe(struct udevice *dev)
 {
 	struct bcm2835_gpios *gpios = dev_get_priv(dev);
-	struct bcm2835_gpio_platdata *plat = dev_get_plat(dev);
+	struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
 	uc_priv->bank_name = "GPIO";
@@ -118,7 +118,7 @@ static int bcm2835_gpio_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static int bcm2835_gpio_of_to_plat(struct udevice *dev)
 {
-	struct bcm2835_gpio_platdata *plat = dev_get_plat(dev);
+	struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
 	fdt_addr_t addr;
 
 	addr = dev_read_addr(dev);
@@ -134,7 +134,7 @@ U_BOOT_DRIVER(gpio_bcm2835) = {
 	.name	= "gpio_bcm2835",
 	.id	= UCLASS_GPIO,
 	.of_to_plat = of_match_ptr(bcm2835_gpio_of_to_plat),
-	.plat_auto	= sizeof(struct bcm2835_gpio_platdata),
+	.plat_auto	= sizeof(struct bcm2835_gpio_plat),
 	.ops	= &gpio_bcm2835_ops,
 	.probe	= bcm2835_gpio_probe,
 	.flags	= DM_FLAG_PRE_RELOC,

drivers/gpio/da8xx_gpio.c

@@ -522,7 +522,7 @@ static const struct dm_gpio_ops gpio_davinci_ops = {
 static int davinci_gpio_probe(struct udevice *dev)
 {
 	struct davinci_gpio_bank *bank = dev_get_priv(dev);
-	struct davinci_gpio_platdata *plat = dev_get_plat(dev);
+	struct davinci_gpio_plat *plat = dev_get_plat(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
@@ -542,7 +542,7 @@ static const struct udevice_id davinci_gpio_ids[] = {
 
 static int davinci_gpio_of_to_plat(struct udevice *dev)
 {
-	struct davinci_gpio_platdata *plat = dev_get_plat(dev);
+	struct davinci_gpio_plat *plat = dev_get_plat(dev);
 	fdt_addr_t addr;
 
 	addr = dev_read_addr(dev);
@@ -560,7 +560,7 @@ U_BOOT_DRIVER(ti_dm6441_gpio) = {
 	.of_to_plat = of_match_ptr(davinci_gpio_of_to_plat),
 	.of_match = davinci_gpio_ids,
 	.bind   = dm_scan_fdt_dev,
-	.plat_auto	= sizeof(struct davinci_gpio_platdata),
+	.plat_auto	= sizeof(struct davinci_gpio_plat),
 	.probe	= davinci_gpio_probe,
 	.priv_auto	= sizeof(struct davinci_gpio_bank),
 };

drivers/gpio/da8xx_gpio.h

@@ -31,7 +31,7 @@ struct davinci_gpio_bank {
 #if CONFIG_IS_ENABLED(DM_GPIO)
 
 /* Information about a GPIO bank */
-struct davinci_gpio_platdata {
+struct davinci_gpio_plat {
 	int bank_index;
 	ulong base;	/* address of registers in physical memory */
 	const char *port_name;