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ARM: vf610: Enable external 32KHz oscillator 

Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
This commit is contained in:
Stefan Agner 2015-04-15 16:24:23 +05:30 committed by Tom Rini
parent c7ea243cc0
commit 8b4f9afac0
3 changed files with 23 additions and 2 deletions
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1
arch/arm/include/asm/arch-vf610/crm_regs.h
View File

@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)

11
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_WDOG_A5 (0x1 << 3)
#define SRC_SRSR_POR_RST (0x1 << 0) #define SRC_SRSR_POR_RST (0x1 << 0)
/* Slow Clock Source Controller Module (SCSC) */
#define SCSC_SOSC_CTR_SOSC_EN 0x1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h> #include <asm/types.h>
@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848]; u16 rsvd3[848];
}; };
/* SCSC */
struct scsc_reg {
u32 sirc_ctr;
u32 sosc_ctr;
};
#endif /* __ASSEMBLER__*/ #endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */ #endif /* __ASM_ARCH_IMX_REGS_H__ */

13
board/freescale/vf610twr/vf610twr.c
View File

@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK); CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
CCM_CCGR3_ANADIG_CTRL_MASK); CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void) int board_init(void)
{ {
struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
/* address of boot parameters */ /* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/*
* Enable external 32K Oscillator
*
* The internal clock experiences significant drift
* so we must use the external oscillator in order
* to maintain correct time in the hwclock
*/
setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
return 0; return 0;
} }