Merge git://git.denx.de/u-boot-sh

arch/arm/dts/r8a7791-koelsch-u-boot.dts

@@ -8,3 +8,7 @@
 
 #include "r8a7791-koelsch.dts"
 #include "r8a7791-u-boot.dtsi"
+
+&scif0 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/r8a7795.dtsi

@@ -1525,6 +1525,14 @@
 			dma-channels = <2>;
 		};
 
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a7795", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a7795";
 			reg = <0 0xee100000 0 0x2000>;

arch/arm/dts/r8a7796.dtsi

@@ -1350,6 +1350,14 @@
 			status = "disabled";
 		};
 
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a7796", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a7796";
 			reg = <0 0xee100000 0 0x2000>;

arch/arm/dts/r8a77965.dtsi

@@ -748,6 +748,14 @@
 			status = "disabled";
 		};
 
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a77965", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a77965";
 			reg = <0 0xee100000 0 0x2000>;

arch/arm/dts/r8a77970-eagle.dts

@@ -17,6 +17,7 @@
 	aliases {
 		serial0 = &scif0;
 		ethernet0 = &avb;
+		spi0 = &rpc;
 	};
 
 	chosen {
@@ -59,6 +60,25 @@
 	};
 };
 
+&rpc {
+	num-cs = <1>;
+	status = "okay";
+	spi-max-frequency = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		status = "okay";
+	};
+};
+
 &scif0 {
 	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";

arch/arm/dts/r8a77970.dtsi

@@ -381,5 +381,13 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a77970", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
 	};
 };

arch/arm/dts/r8a77995.dtsi

@@ -400,5 +400,13 @@
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+
+		rpc: rpc@0xee200000 {
+			compatible = "renesas,rpc-r8a77995", "renesas,rpc";
+			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+			clocks = <&cpg CPG_MOD 917>;
+			bank-width = <2>;
+			status = "disabled";
+		};
 	};
 };

arch/arm/mach-rmobile/Kconfig.32

@@ -47,6 +47,9 @@ config TARGET_KOELSCH
 	bool "Koelsch board"
 	select DM
 	select DM_SERIAL
+	select SUPPORT_SPL
+	select USE_TINY_PRINTF
+	select SPL_TINY_MEMSET
 
 config TARGET_LAGER
 	bool "Lager board"

board/renesas/koelsch/Makefile

@@ -6,4 +6,8 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= koelsch.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y	:= koelsch_spl.o
+else
+obj-y	:= koelsch.o qos.o
+endif

board/renesas/koelsch/koelsch.c

@@ -48,13 +48,7 @@ void s_init(void)
 	qos_init();
 }
 
-#define TMU0_MSTP125	(1 << 25)
+#define TMU0_MSTP125	BIT(25)
-#define SCIF0_MSTP721	(1 << 21)
-#define ETHER_MSTP813	(1 << 13)
-
-#define SDHI0_MSTP314	(1 << 14)
-#define SDHI1_MSTP312	(1 << 12)
-#define SDHI2_MSTP311	(1 << 11)
 
 #define SD1CKCR		0xE6150078
 #define SD2CKCR		0xE615026C
@@ -64,16 +58,6 @@ int board_early_init_f(void)
 {
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 
-	/* SCIF0 */
-	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
-	/* ETHER */
-	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
-	/* SDHI  */
-	mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
-			  SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
-
 	/*
 	 * SD0 clock is set to 97.5MHz by default.
 	 * Set SD1 and SD2 to the 97.5MHz as well.
@@ -84,133 +68,40 @@ int board_early_init_f(void)
 	return 0;
 }
 
-/* LSI pin pull-up control */
+#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
-#define PUPR5 0xe6060114
+
-#define PUPR5_ETH 0x3FFC0000
-#define PUPR5_ETH_MAGIC	(1 << 27)
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	/* Init PFC controller */
+	/* Force ethernet PHY out of reset */
-	r8a7791_pinmux_init();
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
-
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
-	/* ETHER Enable */
+	mdelay(10);
-	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
-	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-	gpio_request(GPIO_FN_ETH_RXD0, NULL);
-	gpio_request(GPIO_FN_ETH_RXD1, NULL);
-	gpio_request(GPIO_FN_ETH_LINK, NULL);
-	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
-	gpio_request(GPIO_FN_ETH_MDIO, NULL);
-	gpio_request(GPIO_FN_ETH_TXD1, NULL);
-	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-	gpio_request(GPIO_FN_ETH_TXD0, NULL);
-	gpio_request(GPIO_FN_ETH_MDC, NULL);
-	gpio_request(GPIO_FN_IRQ0, NULL);
-
-	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
-	gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
-	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
-	gpio_direction_output(GPIO_GP_5_22, 0);
-	mdelay(20);
-	gpio_set_value(GPIO_GP_5_22, 1);
-	udelay(1);
 
 	return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SH_ETHER
-	int ret = -ENODEV;
-	u32 val;
-	unsigned char enetaddr[6];
-
-	ret = sh_eth_initialize(bis);
-	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
-		return ret;
-
-	/* Set Mac address */
-	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
-		enetaddr[2] << 8 | enetaddr[3];
-	writel(val, CXR24);
-
-	val = enetaddr[4] << 8 | enetaddr[5];
-	writel(val, CXR25);
-
-	return ret;
-#else
-	return 0;
-#endif
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
-	gpio_request(GPIO_FN_SD0_DATA0, NULL);
-	gpio_request(GPIO_FN_SD0_DATA1, NULL);
-	gpio_request(GPIO_FN_SD0_DATA2, NULL);
-	gpio_request(GPIO_FN_SD0_DATA3, NULL);
-	gpio_request(GPIO_FN_SD0_CLK, NULL);
-	gpio_request(GPIO_FN_SD0_CMD, NULL);
-	gpio_request(GPIO_FN_SD0_CD, NULL);
-	gpio_request(GPIO_FN_SD2_DATA0, NULL);
-	gpio_request(GPIO_FN_SD2_DATA1, NULL);
-	gpio_request(GPIO_FN_SD2_DATA2, NULL);
-	gpio_request(GPIO_FN_SD2_DATA3, NULL);
-	gpio_request(GPIO_FN_SD2_CLK, NULL);
-	gpio_request(GPIO_FN_SD2_CMD, NULL);
-	gpio_request(GPIO_FN_SD2_CD, NULL);
-
-	/* SDHI 0 */
-	gpio_request(GPIO_GP_7_17, NULL);
-	gpio_request(GPIO_GP_2_12, NULL);
-	gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
-	gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
-
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
-			   SH_SDHI_QUIRK_16BIT_BUF);
-	if (ret)
-		return ret;
-
-	/* SDHI 1 */
-	gpio_request(GPIO_GP_7_18, NULL);
-	gpio_request(GPIO_GP_2_13, NULL);
-	gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
-	gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
-
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
-	if (ret)
-		return ret;
-
-	/* SDHI 2 */
-	gpio_request(GPIO_GP_7_19, NULL);
-	gpio_request(GPIO_GP_2_26, NULL);
-	gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
-	gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
-
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
-	return ret;
-}
-
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
 	return 0;
 }
 
-/* koelsch has KSZ8041NL/RNL */
+int dram_init_banksize(void)
-#define PHY_CONTROL1	0x1E
+{
-#define PHY_LED_MODE	0xC0000
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* Koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC0000
 #define PHY_LED_MODE_ACK	0x4000
 int board_phy_config(struct phy_device *phydev)
 {
@@ -228,22 +119,38 @@ const struct rmobile_sysinfo sysinfo = {
 
 void reset_cpu(ulong addr)
 {
-	u8 val;
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
 
-	i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
-	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	if (ret)
-	val |= 0x02;
+		hang();
-	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
 }
 
-static const struct sh_serial_platdata serial_platdata = {
+enum env_location env_get_location(enum env_operation op, int prio)
-	.base = SCIF0_BASE,
+{
-	.type = PORT_SCIF,
+	const u32 load_magic = 0xb33fc0de;
-	.clk = 14745600,
-	.clk_mode = EXT_CLK,
-};
 
-U_BOOT_DEVICE(koelsch_serials) = {
+	/* Block environment access if loaded using JTAG */
-	.name = "serial_sh",
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
-	.platdata = &serial_platdata,
+	    (op != ENVOP_INIT))
-};
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}

board/renesas/koelsch/koelsch_spl.c

@@ -0,0 +1,410 @@
+/*
+ * board/renesas/koelsch/koelsch_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+
+	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x60000000 },
+		{ 0x0094, 0x60000000 },
+		{ 0x0098, 0x00800200 },
+		{ 0x009c, 0x00000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x000244c8 },
+		{ 0x002c, 0x00000000 },
+		{ 0x0030, 0x00002400 },
+		{ 0x0034, 0x01520000 },
+		{ 0x0038, 0x00724003 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x00000000 },
+		{ 0x0048, 0x00000000 },
+		{ 0x004c, 0x00000000 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000000 },
+		{ 0x0058, 0x00000000 },
+		{ 0x005c, 0x00000000 },
+		{ 0x0160, 0x00000000 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x3bc001e7 },
+		{ 0x0010, 0x5bffffff },
+		{ 0x0014, 0x1ffffffb },
+		{ 0x0018, 0x01bffff0 },
+		{ 0x001c, 0xcf7fffff },
+		{ 0x0074, 0x0381fc00 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0xffffffdf },
+		{ 0x0104, 0xc883c3ff },
+		{ 0x0108, 0x1201f3c9 },
+		{ 0x010c, 0x00000000 },
+		{ 0x0110, 0xffffeb04 },
+		{ 0x0114, 0xc003ffff },
+		{ 0x0118, 0x0800000f },
+		{ 0x011c, 0x001800f0 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x04381000 },
+		{ 0x5000, 0x00000000 },
+		{ 0x5800, 0x000e0000 },
+
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x2000, 0x04381010 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00000000 },
+		{ 0x5000, 0x00400000 },
+		{ 0x5400, 0x00000000 },
+		{ 0x5800, 0x000e0380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000300 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082008 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c481 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fdb6c0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+	}
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+	}
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	int i;
+
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+
+	/* Unknown, likely ES1.0-specific delay */
+	for (i = 0; i < 100000; i++)
+		asm volatile("nop");
+
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}

board/renesas/porter/porter.c

@@ -11,6 +11,7 @@
 #include <malloc.h>
 #include <dm.h>
 #include <dm/platform_data/serial_sh.h>
+#include <environment.h>
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
@@ -136,3 +137,18 @@ void reset_cpu(ulong addr)
 	if (ret)
 		hang();
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}

board/renesas/stout/stout.c

@@ -128,3 +128,18 @@ int board_phy_config(struct phy_device *phydev)
 const struct rmobile_sysinfo sysinfo = {
 	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}

configs/koelsch_defconfig

@@ -1,17 +1,37 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
+CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_R8A7791=y
 CONFIG_TARGET_KOELSCH=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SDRAM=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
@@ -19,21 +39,42 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
 CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y

configs/r8a7795_salvator-x_defconfig

@@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_SALVATOR_X=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

configs/r8a7795_ulcb_defconfig

@@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_ULCB=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

configs/r8a77965_salvator-x_defconfig

@@ -7,6 +7,7 @@ CONFIG_R8A7796=y
 CONFIG_TARGET_SALVATOR_X=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

configs/r8a7796_salvator-x_defconfig

@@ -7,6 +7,7 @@ CONFIG_R8A7796=y
 CONFIG_TARGET_SALVATOR_X=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

configs/r8a7796_ulcb_defconfig

@@ -7,6 +7,7 @@ CONFIG_R8A7796=y
 CONFIG_TARGET_ULCB=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

configs/r8a77970_eagle_defconfig

@@ -7,6 +7,7 @@ CONFIG_R8A77970=y
 CONFIG_TARGET_EAGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
@@ -17,7 +18,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -28,19 +30,21 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
+# CONFIG_MMC is not set
-CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_DM_SPI_FLASH=y
-CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPI_FLASH=y
-CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPI_FLASH_BAR=y
-CONFIG_RENESAS_SDHI=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
@@ -52,6 +56,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y

configs/r8a77995_draak_defconfig

@@ -7,6 +7,7 @@ CONFIG_R8A77995=y
 CONFIG_TARGET_DRAAK=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"

include/configs/eagle.h

@@ -19,6 +19,12 @@
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	0x700000
+
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
 #define CONFIG_SYS_CLK_FREQ	33333333u

include/configs/koelsch.h

@@ -14,15 +14,9 @@
 
 #include "rcar-gen2-common.h"
 
-/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+#define STACK_AREA_SIZE			0x00100000
-#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
+#define LOW_LEVEL_MERAM_STACK \
-#else
-#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
-#endif
-
-#define STACK_AREA_SIZE			0xC000
-#define LOW_LEVEL_MERAM_STACK	\
 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
 
 /* MEMORY */
@@ -41,45 +35,29 @@
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
 
 /* Board Clock */
 #define RMOBILE_XTAL_CLK	20000000u
 #define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
 #define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
+
 #define CONFIG_SYS_TMU_CLK_DIV	4
 
-/* i2c */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
-#define CONFIG_SYS_I2C
+	"fdt_high=0xffffffff\0"		\
-#define CONFIG_SYS_I2C_SH
+	"initrd_high=0xffffffff\0"
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
-#define CONFIG_SYS_I2C_SH_SPEED0	400000
-#define CONFIG_SYS_I2C_SH_SPEED1	400000
-#define CONFIG_SYS_I2C_SH_SPEED2	400000
-#define CONFIG_SH_I2C_DATA_HIGH	4
-#define CONFIG_SH_I2C_DATA_LOW	5
-#define CONFIG_SH_I2C_CLOCK	10000000
 
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+/* SPL support */
-
+#define CONFIG_SPL_TEXT_BASE		0xe6300000
-/* USB */
+#define CONFIG_SPL_STACK		0xe6340000
-#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_SPL_MAX_SIZE		0x4000
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x140000
-
+#ifdef CONFIG_SPL_BUILD
-/* Module stop status bits */
+#define CONFIG_CONS_SCIF0
-/* INTC-RT */
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
-#define CONFIG_SMSTP0_ENA	0x00400000
+#endif
-/* MSIF*/
-#define CONFIG_SMSTP2_ENA	0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA	0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA	0x00200000
-
-/* SD */
-#define CONFIG_SH_SDHI_FREQ	97500000
 
 #endif	/* __KOELSCH_H */