nmhw23: port changes to NXP branch
This commit is contained in:
Andrejs Cainikovs
parent
f3931b64d7
commit
8ca326d9a4
|
|
@ -23,6 +23,9 @@
|
|||
*.patch
|
||||
*.cfgtmp
|
||||
|
||||
# Links
|
||||
/board/netmodule/common
|
||||
|
||||
# host programs on Cygwin
|
||||
*.exe
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,25 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2017 NXP
|
||||
* Copyright 2019 NetModule AG
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-imx8dx.dtsi"
|
||||
#include "fsl-imx8qxp-mek-u-boot.dtsi"
|
||||
/* First 128KB is for PSCI ATF. */
|
||||
/* Last 127M is for M4/RPMSG */
|
||||
/memreserve/ 0x80000000 0x08000000;
|
||||
|
||||
#include "fsl-imx8qxp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NetModule NMHW23";
|
||||
|
|
@ -21,10 +34,6 @@
|
|||
stdout-path = &lpuart0;
|
||||
};
|
||||
|
||||
pmu {
|
||||
interrupt-affinity = <&A35_0>, <&A35_1>;
|
||||
};
|
||||
|
||||
spi3: soft-spi3 {
|
||||
compatible = "spi-gpio";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -48,6 +57,7 @@
|
|||
gpio-reset-sw = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
|
|
@ -55,60 +65,91 @@
|
|||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx8-nmhw23 {
|
||||
pinctrl_hog: hog_grp {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c
|
||||
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
|
||||
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpuart0: lpuart0_grp {
|
||||
fsl,pins = <
|
||||
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
|
||||
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
|
||||
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
|
||||
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1_grp {
|
||||
fsl,pins = <
|
||||
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
|
||||
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
|
||||
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
|
||||
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
|
||||
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
|
||||
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
|
||||
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
|
||||
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
|
||||
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
|
||||
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
|
||||
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
|
||||
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
|
||||
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
|
||||
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
|
||||
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
|
||||
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
|
||||
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
|
||||
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
|
||||
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
|
||||
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
|
||||
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
|
||||
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1_100mhz_grp {
|
||||
fsl,pins = <
|
||||
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
|
||||
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
|
||||
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
|
||||
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
|
||||
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
|
||||
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
|
||||
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
|
||||
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
|
||||
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
|
||||
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
|
||||
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1_200mhz_grp {
|
||||
fsl,pins = <
|
||||
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
|
||||
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
|
||||
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
|
||||
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
|
||||
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
|
||||
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
|
||||
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
|
||||
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
|
||||
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
|
||||
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
|
||||
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spi3: spi3_grp {
|
||||
fsl,pins = <
|
||||
SC_P_SPI3_SCK_LSIO_GPIO0_IO13 0x00000041
|
||||
SC_P_SPI3_SDO_LSIO_GPIO0_IO14 0x00000041
|
||||
SC_P_SPI3_SDI_LSIO_GPIO0_IO15 0x00000041
|
||||
SC_P_SPI3_CS0_LSIO_GPIO0_IO16 0x00000061
|
||||
SC_P_SPI3_SCK_LSIO_GPIO0_IO13 0x00000041
|
||||
SC_P_SPI3_SDO_LSIO_GPIO0_IO14 0x00000041
|
||||
SC_P_SPI3_SDI_LSIO_GPIO0_IO15 0x00000041
|
||||
SC_P_SPI3_CS0_LSIO_GPIO0_IO16 0x00000061
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_hsm: reset_hsm_grp {
|
||||
fsl,pins = <
|
||||
SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000060
|
||||
SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000060
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_phy: reset_phy_grp {
|
||||
fsl,pins = <
|
||||
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000021
|
||||
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000021
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_sw: reset_sw_grp {
|
||||
fsl,pins = <
|
||||
SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 0x00000060
|
||||
SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 0x00000060
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -130,21 +171,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
&A35_0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&lpuart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -174,3 +219,13 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,32 +1,63 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2017-2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <environment.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <i2c.h>
|
||||
#include "pca953x.h"
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/mach-imx/sci/sci.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <dm.h>
|
||||
#include <imx8_hsio.h>
|
||||
#include <usb.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/video.h>
|
||||
#include <asm/arch/video_common.h>
|
||||
#include <power-domain.h>
|
||||
#include "../../freescale/common/tcpc.h"
|
||||
#include <cdns3-uboot.h>
|
||||
#include <asm/arch/lpcg.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
|
||||
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
|
||||
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart0_pads[] = {
|
||||
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
|
|
@ -40,46 +71,120 @@ static void setup_iomux_uart(void)
|
|||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
int ret;
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
sc_pm_clock_rate_t rate = 80000000;
|
||||
sc_ipc_t ipcHndl = 0;
|
||||
sc_err_t sciErr = 0;
|
||||
|
||||
ipcHndl = gd->arch.ipc_channel_handle;
|
||||
|
||||
/* Power up UART0 */
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON);
|
||||
if (sciErr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
sc_pm_clock_rate_t rate = 80000000;
|
||||
sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate);
|
||||
if (sciErr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
/* Enable UART0 clock root */
|
||||
ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false);
|
||||
if (sciErr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
LPCG_AllClockOn(LPUART_0_LPCG);
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_DM_GPIO)
|
||||
static void board_gpio_init(void)
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC1_BASE_ADDR, 0, 8 };
|
||||
|
||||
static iomux_cfg_t emmc0[] = {
|
||||
SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/* TODO */
|
||||
int ret;
|
||||
struct power_domain pd;
|
||||
|
||||
if (!power_domain_lookup_name("conn_sdhc0", &pd))
|
||||
{
|
||||
power_domain_on(&pd);
|
||||
}
|
||||
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
|
||||
init_clk_usdhc(0);
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
|
||||
if (ret)
|
||||
{
|
||||
printf("Warning: failed to initialize mmc\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
/* eMMC */
|
||||
if (cfg->esdhc_base == USDHC1_BASE_ADDR)
|
||||
{
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* CONFIG_FSL_ESDHC */
|
||||
|
||||
#ifdef CONFIG_BOOTP_VENDOREX
|
||||
u8 *dhcp_vendorex_prep(u8 *e)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
u8 *dhcp_vendorex_proc(u8 *e)
|
||||
{
|
||||
/* Suppress NETBIOS related unhandled option warnings */
|
||||
if (*e == 46)
|
||||
{
|
||||
return e;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#else
|
||||
static inline void board_gpio_init(void) {}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
|
|
@ -90,35 +195,271 @@ int board_phy_config(struct phy_device *phydev)
|
|||
}
|
||||
#endif
|
||||
|
||||
void build_info(void)
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
u32 sc_build = 0, sc_commit = 0;
|
||||
int ret;
|
||||
struct gpio_desc desc;
|
||||
|
||||
/* Get SCFW build and commit id */
|
||||
sc_misc_build_info(-1, &sc_build, &sc_commit);
|
||||
if (!sc_build) {
|
||||
printf("SCFW does not support build info\n");
|
||||
sc_commit = 0; /* Display 0 when the build info is not supported*/
|
||||
}
|
||||
printf("Build: SCFW %x\n", sc_commit);
|
||||
ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
ret = dm_gpio_request(&desc, "bb_per_rst_b");
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
|
||||
dm_gpio_set_value(&desc, 0);
|
||||
udelay(50);
|
||||
dm_gpio_set_value(&desc, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: iMX8DX VCU2\n");
|
||||
puts("Board: iMX8QXP MEK\n");
|
||||
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
/* Note: After reloc, ipcHndl will no longer be valid. If handle
|
||||
* returned by sc_ipc_open matches SC_IPC_CH, use this
|
||||
* macro (valid after reloc) for subsequent SCI calls.
|
||||
*/
|
||||
if (gd->arch.ipc_channel_handle != SC_IPC_CH)
|
||||
printf("\nSCI error! Invalid handle\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_HSIO
|
||||
|
||||
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
|
||||
static iomux_cfg_t board_pcie_pins[] = {
|
||||
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
|
||||
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
|
||||
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void imx8qxp_hsio_initialize(void)
|
||||
{
|
||||
struct power_domain pd;
|
||||
int ret;
|
||||
|
||||
if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
|
||||
ret = power_domain_on(&pd);
|
||||
if (ret)
|
||||
printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
|
||||
}
|
||||
|
||||
if (!power_domain_lookup_name("hsio_gpio", &pd)) {
|
||||
ret = power_domain_on(&pd);
|
||||
if (ret)
|
||||
printf("hsio_gpio Power up failed! (error = %d)\n", ret);
|
||||
}
|
||||
|
||||
LPCG_AllClockOn(HSIO_PCIE_X1_LPCG);
|
||||
LPCG_AllClockOn(HSIO_PHY_X1_LPCG);
|
||||
LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG);
|
||||
LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG);
|
||||
LPCG_AllClockOn(HSIO_MISC_LPCG);
|
||||
LPCG_AllClockOn(HSIO_GPIO_LPCG);
|
||||
|
||||
imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
|
||||
}
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
imx8qxp_hsio_initialize();
|
||||
|
||||
/* test the 1 lane mode of the PCIe A controller */
|
||||
mx8qxp_pcie_init();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
|
||||
#ifdef CONFIG_USB_TCPC
|
||||
#define USB_TYPEC_SEL IMX_GPIO_NR(5, 9)
|
||||
static iomux_cfg_t ss_mux_gpio[] = {
|
||||
SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
struct tcpc_port port;
|
||||
struct tcpc_port_config port_config = {
|
||||
.i2c_bus = 1,
|
||||
.addr = 0x50,
|
||||
.port_type = TYPEC_PORT_DFP,
|
||||
};
|
||||
|
||||
void ss_mux_select(enum typec_cc_polarity pol)
|
||||
{
|
||||
if (pol == TYPEC_POLARITY_CC1)
|
||||
gpio_direction_output(USB_TYPEC_SEL, 0);
|
||||
else
|
||||
gpio_direction_output(USB_TYPEC_SEL, 1);
|
||||
}
|
||||
|
||||
static void setup_typec(void)
|
||||
{
|
||||
int ret;
|
||||
struct gpio_desc typec_en_desc;
|
||||
|
||||
imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
|
||||
gpio_request(USB_TYPEC_SEL, "typec_sel");
|
||||
|
||||
ret = dm_gpio_lookup_name("gpio@1a_7", &typec_en_desc);
|
||||
if (ret) {
|
||||
printf("%s lookup gpio@1a_7 failed ret = %d\n", __func__, ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = dm_gpio_request(&typec_en_desc, "typec_en");
|
||||
if (ret) {
|
||||
printf("%s request typec_en failed ret = %d\n", __func__, ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable SS MUX */
|
||||
dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
|
||||
|
||||
tcpc_init(&port, port_config, &ss_mux_select);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_CDNS3_GADGET
|
||||
static struct cdns3_device cdns3_device_data = {
|
||||
.none_core_base = 0x5B110000,
|
||||
.xhci_base = 0x5B130000,
|
||||
.dev_base = 0x5B140000,
|
||||
.phy_base = 0x5B160000,
|
||||
.otg_base = 0x5B120000,
|
||||
.dr_mode = USB_DR_MODE_PERIPHERAL,
|
||||
.index = 1,
|
||||
};
|
||||
|
||||
int usb_gadget_handle_interrupts(int index)
|
||||
{
|
||||
cdns3_uboot_handle_interrupt(index);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (index == 1) {
|
||||
if (init == USB_INIT_HOST) {
|
||||
#ifdef CONFIG_USB_TCPC
|
||||
ret = tcpc_setup_dfp_mode(&port);
|
||||
#endif
|
||||
#ifdef CONFIG_USB_CDNS3_GADGET
|
||||
} else {
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
sc_ipc_t ipcHndl = 0;
|
||||
|
||||
ipcHndl = gd->arch.ipc_channel_handle;
|
||||
|
||||
ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_ON);
|
||||
if (ret != SC_ERR_NONE)
|
||||
printf("conn_usb2 Power up failed! (error = %d)\n", ret);
|
||||
|
||||
ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_ON);
|
||||
if (ret != SC_ERR_NONE)
|
||||
printf("conn_usb2_phy Power up failed! (error = %d)\n", ret);
|
||||
#else
|
||||
struct power_domain pd;
|
||||
int ret;
|
||||
|
||||
/* Power on usb */
|
||||
if (!power_domain_lookup_name("conn_usb2", &pd)) {
|
||||
ret = power_domain_on(&pd);
|
||||
if (ret)
|
||||
printf("conn_usb2 Power up failed! (error = %d)\n", ret);
|
||||
}
|
||||
|
||||
if (!power_domain_lookup_name("conn_usb2_phy", &pd)) {
|
||||
ret = power_domain_on(&pd);
|
||||
if (ret)
|
||||
printf("conn_usb2_phy Power up failed! (error = %d)\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_TCPC
|
||||
ret = tcpc_setup_ufp_mode(&port);
|
||||
printf("%d setufp mode %d\n", index, ret);
|
||||
#endif
|
||||
|
||||
ret = cdns3_uboot_init(&cdns3_device_data);
|
||||
printf("%d cdns3_uboot_initmode %d\n", index, ret);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
int board_usb_cleanup(int index, enum usb_init_type init)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (index == 1) {
|
||||
if (init == USB_INIT_HOST) {
|
||||
#ifdef CONFIG_USB_TCPC
|
||||
ret = tcpc_disable_src_vbus(&port);
|
||||
#endif
|
||||
#ifdef CONFIG_USB_CDNS3_GADGET
|
||||
} else {
|
||||
cdns3_uboot_exit(1);
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
sc_ipc_t ipcHndl = 0;
|
||||
|
||||
ipcHndl = gd->arch.ipc_channel_handle;
|
||||
|
||||
ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_OFF);
|
||||
if (ret != SC_ERR_NONE)
|
||||
printf("conn_usb2 Power down failed! (error = %d)\n", ret);
|
||||
|
||||
ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF);
|
||||
if (ret != SC_ERR_NONE)
|
||||
printf("conn_usb2_phy Power down failed! (error = %d)\n", ret);
|
||||
#else
|
||||
struct power_domain pd;
|
||||
int ret;
|
||||
|
||||
/* Power off usb */
|
||||
if (!power_domain_lookup_name("conn_usb2", &pd)) {
|
||||
ret = power_domain_off(&pd);
|
||||
if (ret)
|
||||
printf("conn_usb2 Power down failed! (error = %d)\n", ret);
|
||||
}
|
||||
|
||||
if (!power_domain_lookup_name("conn_usb2_phy", &pd)) {
|
||||
ret = power_domain_off(&pd);
|
||||
if (ret)
|
||||
printf("conn_usb2_phy Power down failed! (error = %d)\n", ret);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct udevice *sja1105;
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
board_gpio_init();
|
||||
#endif
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_MISC, "sja1105", &sja1105);
|
||||
if (ret)
|
||||
|
|
@ -130,9 +471,26 @@ int board_init(void)
|
|||
printf("Net: SJA1105 switch found.\n");
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
|
||||
setup_typec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_quiesce_devices()
|
||||
{
|
||||
const char *power_on_devices[] = {
|
||||
"dma_lpuart0",
|
||||
|
||||
/* HIFI DSP boot */
|
||||
"audio_sai0",
|
||||
"audio_ocram",
|
||||
};
|
||||
|
||||
power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
|
|
@ -143,7 +501,10 @@ void detail_board_ddr_info(void)
|
|||
*/
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* TODO */
|
||||
puts("SCI reboot request");
|
||||
sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
|
||||
while (1)
|
||||
putc('.');
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
|
|
@ -165,5 +526,14 @@ int board_late_init(void)
|
|||
env_set("board_rev", "iMX8DX");
|
||||
#endif
|
||||
|
||||
env_set("sec_boot", "no");
|
||||
#ifdef CONFIG_AHAB_BOOT
|
||||
env_set("sec_boot", "yes");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2019 NetModule AG
|
||||
*
|
||||
* Refer doc/README.imx8image for more details about how-to configure
|
||||
* and create imx8image boot image
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
/* Boot from SD, sector size 0x400 */
|
||||
BOOT_FROM SD 0x400
|
||||
/* SoC type IMX8QX */
|
||||
SOC_TYPE IMX8QX
|
||||
/* Append seco container image */
|
||||
APPEND ahab-container.img
|
||||
/* Create the 2nd container */
|
||||
CONTAINER
|
||||
/* Add scfw image with exec attribute */
|
||||
IMAGE SCU imx8-nmhw23-scfw.bin
|
||||
/* Add ATF image with exec attribute */
|
||||
IMAGE A35 spl/u-boot-spl.bin 0x00100000
|
||||
|
|
@ -4,6 +4,17 @@
|
|||
|
||||
set -e
|
||||
|
||||
# Create vendor common dir link
|
||||
|
||||
if [ ! -d "board/netmodule/common" ]; then
|
||||
ln -s `realpath board/freescale/common` board/netmodule/common
|
||||
fi
|
||||
|
||||
# Build boot image
|
||||
|
||||
make imx8_nmhw23_defconfig
|
||||
make
|
||||
|
||||
# Checkout imx-image git if not present
|
||||
|
||||
if [ ! -d "imx-mkimage.git" ]; then
|
||||
|
|
@ -13,17 +24,13 @@ if [ ! -d "imx-mkimage.git" ]; then
|
|||
ln -s `realpath imx8-nmhw23-scfw.bin` imx-mkimage.git/iMX8QX/scfw_tcm.bin
|
||||
fi
|
||||
|
||||
# Build boot image
|
||||
|
||||
make imx8_nmhw23_defconfig
|
||||
make
|
||||
|
||||
# Generate boot image
|
||||
|
||||
cp u-boot.bin imx-mkimage.git/iMX8QX/
|
||||
cd imx-mkimage.git
|
||||
make SOC=iMX8QX flash
|
||||
cd ..
|
||||
mv imx-mkimage.git/iMX8QX/flash.bin .
|
||||
cp imx-mkimage.git/iMX8QX/flash.bin .
|
||||
|
||||
# Generate eMMC/SD image
|
||||
|
||||
|
|
|
|||
|
|
@ -319,8 +319,12 @@ const char *bootdelay_process(void)
|
|||
set_default_env("Use default environment for \
|
||||
mfgtools\n");
|
||||
} else if (is_boot_from_usb()) {
|
||||
#ifdef CONFIG_CMD_FASTBOOT
|
||||
printf("Boot from USB for uuu\n");
|
||||
env_set("bootcmd", "fastboot 0");
|
||||
#else
|
||||
printf("Boot from USB\n");
|
||||
#endif
|
||||
} else {
|
||||
printf("Normal Boot\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,75 +1,90 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_IMX8_NMHW23=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/netmodule/imx8_nmhw23/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_CMD_CPU=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8_nmhw23"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_IMX8=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_TARGET_IMX8_NMHW23=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||
CONFIG_CMD_IMPORTENV=n
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_DM=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_IMX8=y
|
||||
|
||||
CONFIG_DM_USB=y
|
||||
|
||||
CONFIG_USB=y
|
||||
# CONFIG_USB_TCPC is not set
|
||||
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
|
||||
CONFIG_USB_CDNS3=y
|
||||
CONFIG_USB_CDNS3_GADGET=y
|
||||
CONFIG_USB_GADGET_DUALSPEED=y
|
||||
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_4BYTES_ADDR=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_CMD_SF=y
|
||||
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_SC_THERMAL=y
|
||||
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
|
||||
CONFIG_SMC_FUSE=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
|
||||
CONFIG_SYS_I2C_IMX_VIRT_I2C=y
|
||||
CONFIG_I2C_MUX_IMX_VIRT=y
|
||||
CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
|
||||
|
||||
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
|
||||
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
|
||||
|
||||
CONFIG_SOFT_SPI=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_SJA1105=y
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <miiphy.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include "fec_mxc.h"
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
|
|
@ -25,6 +24,9 @@
|
|||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#include "fec_mxc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -1258,6 +1260,21 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
/* FEC GPIO reset */
|
||||
static void fec_gpio_reset(struct fec_priv *priv)
|
||||
{
|
||||
debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
|
||||
if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
|
||||
dm_gpio_set_value(&priv->phy_reset_gpio, 1);
|
||||
mdelay(priv->reset_delay);
|
||||
dm_gpio_set_value(&priv->phy_reset_gpio, 0);
|
||||
if (priv->reset_post_delay)
|
||||
mdelay(priv->reset_post_delay);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int fecmxc_probe(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
|
|
@ -1278,6 +1295,9 @@ static int fecmxc_probe(struct udevice *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
fec_gpio_reset(priv);
|
||||
#endif
|
||||
/* Reset chip. */
|
||||
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
|
||||
&priv->eth->ecntrl);
|
||||
|
|
@ -1335,6 +1355,7 @@ static int fecmxc_remove(struct udevice *dev)
|
|||
|
||||
static int fecmxc_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
int ret = 0;
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct fec_priv *priv = dev_get_priv(dev);
|
||||
const char *phy_mode;
|
||||
|
|
@ -1352,10 +1373,28 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* TODO
|
||||
* Need to get the reset-gpio and related properties from DT
|
||||
* and implemet the enet reset code on .probe call
|
||||
*/
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
|
||||
&priv->phy_reset_gpio, GPIOD_IS_OUT);
|
||||
if (ret < 0)
|
||||
return 0; /* property is optional, don't return error! */
|
||||
|
||||
priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
|
||||
if (priv->reset_delay > 1000) {
|
||||
printf("FEC MXC: phy reset duration should be <= 1000ms\n");
|
||||
/* property value wrong, use default value */
|
||||
priv->reset_delay = 1;
|
||||
}
|
||||
|
||||
priv->reset_post_delay = dev_read_u32_default(dev,
|
||||
"phy-reset-post-delay",
|
||||
0);
|
||||
if (priv->reset_post_delay > 1000) {
|
||||
printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
|
||||
/* property value wrong, use default value */
|
||||
priv->reset_post_delay = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -251,7 +251,11 @@ struct fec_priv {
|
|||
int phy_id;
|
||||
int (*mii_postcall)(int);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
struct gpio_desc phy_reset_gpio;
|
||||
uint32_t reset_delay;
|
||||
uint32_t reset_post_delay;
|
||||
#endif
|
||||
#ifdef CONFIG_DM_ETH
|
||||
u32 interface;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2019 NetModule AG
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX8_NMHW23_H
|
||||
|
|
@ -10,35 +10,66 @@
|
|||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#include "imx_env.h"
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
|
||||
#ifdef CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#endif
|
||||
|
||||
#define CONFIG_PARSE_CONTAINER
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000
|
||||
|
||||
/*
|
||||
* 0x08081000 - 0x08180FFF is for m4_0 xip image,
|
||||
* So 3rd container image may start from 0x8181000
|
||||
*/
|
||||
#define CONFIG_SYS_UBOOT_BASE 0x08181000
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
|
||||
|
||||
|
||||
#define CONFIG_SPL_WATCHDOG_SUPPORT
|
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x013E000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00138000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */
|
||||
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_MALLOC_F_ADDR 0x00120000
|
||||
#define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
||||
|
||||
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
|
||||
|
||||
#define CONFIG_OF_EMBED
|
||||
#define CONFIG_ATF_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SYS_ATF_START 0x80000000
|
||||
/* #define CONFIG_FIT */
|
||||
|
||||
/* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
|
||||
#define SC_IPC_CH SC_IPC_AP_CH0
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
#define CONFIG_CMD_READ
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
|
@ -59,42 +90,103 @@
|
|||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
#define CONFIG_FSL_HSIO
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
/* FUSE command */
|
||||
#define CONFIG_CMD_FUSE
|
||||
|
||||
/* GPIO configs */
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/* ENET Config */
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define IMX_FEC_BASE 0x5B040000
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
|
||||
#define CONFIG_LIB_RAND
|
||||
#define CONFIG_NET_RANDOM_ETHADDR
|
||||
|
||||
#define CONFIG_BOOTP_VENDOREX
|
||||
|
||||
#ifdef CONFIG_AHAB_BOOT
|
||||
#define AHAB_ENV "sec_boot=yes\0"
|
||||
#else
|
||||
#define AHAB_ENV "sec_boot=no\0"
|
||||
#endif
|
||||
|
||||
/* Boot M4 */
|
||||
#define M4_BOOT_ENV \
|
||||
"m4_0_image=m4_0.bin\0" \
|
||||
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
|
||||
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"initrd_addr=0x83100000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"emmc_dev=0\0" \
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
M4_BOOT_ENV \
|
||||
AHAB_ENV \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"earlycon=lpuart32,0x5a060000\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"cntr_addr=0x98000000\0" \
|
||||
"cntr_file=os_cntr_signed.bin\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=netmodule-imx8-nmhw23.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"fdt_file=undefined\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
|
||||
"auth_os=auth_cntr ${cntr_addr}\0" \
|
||||
"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"if test ${sec_boot} = yes; then " \
|
||||
"if run auth_os; then " \
|
||||
"run boot_os; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"echo ERR: failed to authenticate; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"run boot_os; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
|
|
@ -104,60 +196,83 @@
|
|||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"if test ${sec_boot} = yes; then " \
|
||||
"${get_cmd} ${cntr_addr} ${cntr_file}; " \
|
||||
"if run auth_os; then " \
|
||||
"run boot_os; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"echo ERR: failed to authenticate; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"run boot_os; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;" \
|
||||
"fi;\0"
|
||||
|
||||
/*
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"if test ${sec_boot} = yes; then " \
|
||||
"if run loadcntr; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
*/
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80280000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_32M
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||
|
||||
|
||||
/* Default environment is in SD */
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#else
|
||||
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* eMMC */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
|
||||
|
||||
/* 1 Bank, 1GB */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define CONFIG_NR_DRAM_BANKS 8
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GB DDR */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
|
||||
#define PHYS_SDRAM_2 0
|
||||
#define PHYS_SDRAM_2_SIZE 0
|
||||
|
||||
/* Memory test */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (PHYS_SDRAM_1_SIZE >> 1))
|
||||
|
||||
|
|
@ -169,15 +284,59 @@
|
|||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
/* Networking */
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
#ifndef CONFIG_DM_PCA953X
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
#endif
|
||||
|
||||
#define CONFIG_IMX_SMMU
|
||||
|
||||
/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
|
||||
#ifdef CONFIG_FSL_FSPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define FSL_FSPI_FLASH_SIZE SZ_64M
|
||||
#define FSL_FSPI_FLASH_NUM 1
|
||||
#define FSPI0_BASE_ADDR 0x5d120000
|
||||
#define FSPI0_AMBA_BASE 0
|
||||
#define CONFIG_SYS_FSL_FSPI_AHB
|
||||
#endif
|
||||
|
||||
#define CONFIG_SERIAL_TAG
|
||||
|
||||
/* USB Config */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USBD_HS
|
||||
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#define CONFIG_USB_GADGET_MASS_STORAGE
|
||||
#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
|
||||
#define CONFIG_USB_EHCI_HCD
|
||||
#endif
|
||||
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
/* USB OTG controller configs */
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#endif
|
||||
|
||||
#define CONFIG_OF_SYSTEM_SETUP
|
||||
|
||||
#endif /* __IMX8_NMHW23_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue