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Coding Style cleanup

This commit is contained in:
Wolfgang Denk 2006-03-12 02:55:22 +01:00
parent 1264b4050c
commit 8e7b703a62
35 changed files with 482 additions and 500 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CHANGELOG
View File

@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Coding Style cleanup
* Avoid dereferencing NULL in find_cmd() if no valid commands were found * Avoid dereferencing NULL in find_cmd() if no valid commands were found
Patch by Andrew Dyer, 13 Jun 2005 Patch by Andrew Dyer, 13 Jun 2005

1
board/ezkit533/config.mk
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@ -23,4 +23,3 @@
TEXT_BASE = 0x01FC0000 TEXT_BASE = 0x01FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR) PLATFORM_CPPFLAGS += -I$(TOPDIR)

14
board/ezkit533/flash.c
View File

@ -142,15 +142,15 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
int prot,sect; int prot,sect;
prot = 0; prot = 0;
for (sect = s_first; sect <= s_last; ++sect) { for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) if (info->protect[sect])
prot++; prot++;
} }
if (prot) if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot); printf ("- Warning: %d protected sectors will not be erased!\n", prot);
else else
printf ("\n"); printf ("\n");
cnt = s_last - s_first + 1; cnt = s_last - s_first + 1;

1
board/ezkit533/psd4256.h
View File

@ -65,4 +65,3 @@
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ #define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ #define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ #define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */

1
board/ezkit533/u-boot.lds
View File

@ -146,4 +146,3 @@ SECTIONS
_end = . ; _end = . ;
PROVIDE (end = .); PROVIDE (end = .);
} }

1
board/stamp/config.mk
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@ -23,4 +23,3 @@
TEXT_BASE = 0x07FC0000 TEXT_BASE = 0x07FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR) PLATFORM_CPPFLAGS += -I$(TOPDIR)

215
board/stamp/stamp.c
View File

@ -38,55 +38,55 @@
# define SHOW_BOOT_PROGRESS(arg) # define SHOW_BOOT_PROGRESS(arg)
#endif #endif
int checkboard(void) int checkboard (void)
{ {
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
printf("Board: ADI BF533 Stamp board\n"); printf ("Board: ADI BF533 Stamp board\n");
printf(" Support: http://blackfin.uclinux.org/\n"); printf (" Support: http://blackfin.uclinux.org/\n");
printf(" Richard Klingler <richard@uclinux.net>\n"); printf (" Richard Klingler <richard@uclinux.net>\n");
return 0; return 0;
} }
long int initdram(int board_type) long int initdram (int board_type)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG #ifdef DEBUG
printf("SDRAM attributes:\n"); printf ("SDRAM attributes:\n");
printf(" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11), "CAS Latency:%d cycles\n",
(SDRAM_tRAS >> 6), ( SDRAM_tWR >> 19), (SDRAM_CL >> 2 )); (SDRAM_tRCD >> 15),
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); (SDRAM_tRP >> 11),
printf("Bank size = %d MB\n", 128); (SDRAM_tRAS >> 6),
(SDRAM_tWR >> 19),
(SDRAM_CL >> 2));
printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf ("Bank size = %d MB\n", 128);
#endif #endif
gd->bd->bi_memstart = CFG_SDRAM_BASE; gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return (gd->bd->bi_memsize); return (gd->bd->bi_memsize);
} }
void swap_to(int device_id) void swap_to (int device_id)
{ {
if (device_id == ETHERNET) if (device_id == ETHERNET) {
{
*pFIO_DIR = PF0; *pFIO_DIR = PF0;
asm("ssync;"); asm ("ssync;");
*pFIO_FLAG_S = PF0; *pFIO_FLAG_S = PF0;
asm("ssync;"); asm ("ssync;");
} } else if (device_id == FLASH) {
else if (device_id == FLASH)
{
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
*pFIO_FLAG_S = (PF4 | PF3 | PF2 ); *pFIO_FLAG_S = (PF4 | PF3 | PF2);
*pFIO_MASKA_D = (PF8 | PF6 | PF5); *pFIO_MASKA_D = (PF8 | PF6 | PF5);
*pFIO_MASKB_D = (PF7); *pFIO_MASKB_D = (PF7);
*pFIO_POLAR = (PF8 | PF6 | PF5 ); *pFIO_POLAR = (PF8 | PF6 | PF5);
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5); *pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
*pFIO_FLAG_D = (PF4 | PF3 | PF2 ); *pFIO_FLAG_D = (PF4 | PF3 | PF2);
asm("ssync;"); asm ("ssync;");
} } else {
else { printf ("Unknown bank to switch\n");
printf("Unknown bank to switch\n");
} }
return; return;
@ -94,7 +94,7 @@ void swap_to(int device_id)
#if defined(CONFIG_MISC_INIT_R) #if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */ /* miscellaneous platform dependent initialisations */
int misc_init_r(void) int misc_init_r (void)
{ {
int i; int i;
int cf_stat = 0; int cf_stat = 0;
@ -102,40 +102,39 @@ int misc_init_r(void)
/* Check whether CF card is inserted */ /* Check whether CF card is inserted */
*pFIO_EDGE = FIO_EDGE_CF_BITS; *pFIO_EDGE = FIO_EDGE_CF_BITS;
*pFIO_POLAR = FIO_POLAR_CF_BITS; *pFIO_POLAR = FIO_POLAR_CF_BITS;
for (i=0; i < 0x300 ; i++) asm("nop;"); for (i = 0; i < 0x300; i++)
asm ("nop;");
if ( (*pFIO_FLAG_S) & CF_STAT_BITS) if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
{
cf_stat = 0; cf_stat = 0;
} } else {
else
{
cf_stat = 1; cf_stat = 1;
} }
*pFIO_EDGE = FIO_EDGE_BITS; *pFIO_EDGE = FIO_EDGE_BITS;
*pFIO_POLAR = FIO_POLAR_BITS; *pFIO_POLAR = FIO_POLAR_BITS;
if (cf_stat) if (cf_stat) {
{ printf ("Booting from COMPACT flash\n");
printf ("Booting from COMPACT flash\n");
/* Set cycle time for CF */ /* Set cycle time for CF */
*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL; *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
for (i=0; i < 0x1000 ; i++) asm("nop;"); for (i = 0; i < 0x1000; i++)
for (i=0; i < 0x1000 ; i++) asm("nop;"); asm ("nop;");
for (i=0; i < 0x1000 ; i++) asm("nop;"); for (i = 0; i < 0x1000; i++)
asm ("nop;");
for (i = 0; i < 0x1000; i++)
asm ("nop;");
serial_setbrg(); serial_setbrg ();
ide_init(); ide_init ();
setenv ("bootargs", ""); setenv ("bootargs", "");
setenv ("bootcmd", "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000" ); setenv ("bootcmd",
} "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
else } else {
{
printf ("Booting from FLASH\n"); printf ("Booting from FLASH\n");
} }
@ -145,7 +144,7 @@ int misc_init_r(void)
#ifdef CONFIG_STAMP_CF #ifdef CONFIG_STAMP_CF
void cf_outb(unsigned char val, volatile unsigned char* addr) void cf_outb (unsigned char val, volatile unsigned char *addr)
{ {
/* /*
* Set PF1 PF0 respectively to 0 1 to divert address * Set PF1 PF0 respectively to 0 1 to divert address
@ -153,126 +152,124 @@ void cf_outb(unsigned char val, volatile unsigned char* addr)
*/ */
*pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1; *pFIO_FLAG_C = CF_PF1;
asm("ssync;"); asm ("ssync;");
*(addr) = val; *(addr) = val;
asm("ssync;"); asm ("ssync;");
/* Setback PF1 PF0 to 0 0 to address external /* Setback PF1 PF0 to 0 0 to address external
* memory banks */ * memory banks */
*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0; *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
asm("ssync;"); asm ("ssync;");
} }
unsigned char cf_inb(volatile unsigned char *addr) unsigned char cf_inb (volatile unsigned char *addr)
{ {
volatile unsigned char c; volatile unsigned char c;
*pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1; *pFIO_FLAG_C = CF_PF1;
asm("ssync;"); asm ("ssync;");
c = *(addr); c = *(addr);
asm("ssync;"); asm ("ssync;");
*pFIO_FLAG_C = CF_PF1_PF0; *pFIO_FLAG_C = CF_PF1_PF0;
asm("ssync;"); asm ("ssync;");
return c; return c;
} }
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
{ {
int i; int i;
*pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1; *pFIO_FLAG_C = CF_PF1;
asm("ssync;"); asm ("ssync;");
for (i = 0;i < words; i++) for (i = 0; i < words; i++) {
{
*(sect_buf + i) = *(addr); *(sect_buf + i) = *(addr);
asm("ssync;"); asm ("ssync;");
} }
*pFIO_FLAG_C = CF_PF1_PF0; *pFIO_FLAG_C = CF_PF1_PF0;
asm("ssync;"); asm ("ssync;");
} }
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
{ {
int i; int i;
*pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1; *pFIO_FLAG_C = CF_PF1;
asm("ssync;"); asm ("ssync;");
for (i = 0;i < words; i++) for (i = 0; i < words; i++) {
{
*(addr) = *(sect_buf + i); *(addr) = *(sect_buf + i);
asm("ssync;"); asm ("ssync;");
} }
*pFIO_FLAG_C = CF_PF1_PF0; *pFIO_FLAG_C = CF_PF1_PF0;
asm("ssync;"); asm ("ssync;");
} }
#endif #endif
void stamp_led_set(int LED1, int LED2, int LED3) void stamp_led_set (int LED1, int LED2, int LED3)
{ {
*pFIO_INEN &= ~( PF2 | PF3 | PF4); *pFIO_INEN &= ~(PF2 | PF3 | PF4);
*pFIO_DIR |= ( PF2 | PF3 | PF4); *pFIO_DIR |= (PF2 | PF3 | PF4);
if(LED1 == STATUS_LED_OFF) if (LED1 == STATUS_LED_OFF)
*pFIO_FLAG_S = PF2; *pFIO_FLAG_S = PF2;
else else
*pFIO_FLAG_C = PF2; *pFIO_FLAG_C = PF2;
if(LED2 == STATUS_LED_OFF) if (LED2 == STATUS_LED_OFF)
*pFIO_FLAG_S = PF3; *pFIO_FLAG_S = PF3;
else else
*pFIO_FLAG_C = PF3; *pFIO_FLAG_C = PF3;
if(LED3 == STATUS_LED_OFF) if (LED3 == STATUS_LED_OFF)
*pFIO_FLAG_S = PF4; *pFIO_FLAG_S = PF4;
else else
*pFIO_FLAG_C = PF4; *pFIO_FLAG_C = PF4;
asm("ssync;"); asm ("ssync;");
} }
void show_boot_progress(int status) void show_boot_progress (int status)
{ {
switch(status){ switch (status) {
case 1: case 1:
stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_ON); stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
break; break;
case 2: case 2:
stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_OFF); stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
break; break;
case 3: case 3:
stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_ON); stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
break; break;
case 4: case 4:
stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_OFF); stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
break; break;
case 5: case 5:
case 6: case 6:
stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_ON); stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
break; break;
case 7: case 7:
case 8: case 8:
stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_OFF); stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
break; break;
case 9: case 9:
case 10: case 10:
case 11: case 11:
case 12: case 12:
case 13: case 13:
case 14: case 14:
case 15: case 15:
stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_OFF); stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
break; STATUS_LED_OFF);
default: break;
stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_ON); default:
break; stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
break;
} }
} }

1
board/stamp/u-boot.lds
View File

@ -145,4 +145,3 @@ SECTIONS
_end = . ; _end = . ;
PROVIDE (end = .); PROVIDE (end = .);
} }

122
cpu/bf533/cache.S
View File

@ -22,88 +22,88 @@ ENTRY(blackfin_icache_flush_range)
ENTRY(blackfin_dcache_flush_range) ENTRY(blackfin_dcache_flush_range)
R2 = -32; R2 = -32;
R2 = R0 & R2; R2 = R0 & R2;
P0 = R2; P0 = R2;
P1 = R1; P1 = R1;
CSYNC; CSYNC;
1: 1:
FLUSH[P0++]; FLUSH[P0++];
CC = P0 < P1(iu); CC = P0 < P1(iu);
IF CC JUMP 1b(bp); IF CC JUMP 1b(bp);
FLUSH[P0]; FLUSH[P0];
SSYNC; SSYNC;
RTS; RTS;
ENTRY(_icache_invalidate) ENTRY(_icache_invalidate)
ENTRY(invalidate_entire_icache) ENTRY(invalidate_entire_icache)
[--SP] = ( R7:5); [--SP] = ( R7:5);
P0.L = (IMEM_CONTROL & 0xFFFF); P0.L = (IMEM_CONTROL & 0xFFFF);
P0.H = (IMEM_CONTROL >> 16); P0.H = (IMEM_CONTROL >> 16);
R7 = [P0]; R7 = [P0];
/* Clear the IMC bit , All valid bits in the instruction /* Clear the IMC bit , All valid bits in the instruction
* cache are set to the invalid state * cache are set to the invalid state
*/ */
BITCLR(R7,IMC_P); BITCLR(R7,IMC_P);
CLI R6; CLI R6;
SSYNC; /* SSYNC required before invalidating cache. */ SSYNC; /* SSYNC required before invalidating cache. */
.align 8; .align 8;
[P0] = R7; [P0] = R7;
SSYNC; SSYNC;
STI R6; STI R6;
/* Configures the instruction cache agian */ /* Configures the instruction cache agian */
R6 = (IMC | ENICPLB); R6 = (IMC | ENICPLB);
R7 = R7 | R6; R7 = R7 | R6;
CLI R6; CLI R6;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8; .align 8;
[P0] = R7; [P0] = R7;
SSYNC; SSYNC;
STI R6; STI R6;
( R7:5) = [SP++]; ( R7:5) = [SP++];
RTS; RTS;
/* Invalidate the Entire Data cache by /* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits * clearing DMC[1:0] bits
*/ */
ENTRY(invalidate_entire_dcache) ENTRY(invalidate_entire_dcache)
ENTRY(_dcache_invalidate) ENTRY(_dcache_invalidate)
[--SP] = ( R7:6); [--SP] = ( R7:6);
P0.L = (DMEM_CONTROL & 0xFFFF); P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16); P0.H = (DMEM_CONTROL >> 16);
R7 = [P0]; R7 = [P0];
/* Clear the DMC[1:0] bits, All valid bits in the data /* Clear the DMC[1:0] bits, All valid bits in the data
* cache are set to the invalid state * cache are set to the invalid state
*/ */
BITCLR(R7,DMC0_P); BITCLR(R7,DMC0_P);
BITCLR(R7,DMC1_P); BITCLR(R7,DMC1_P);
CLI R6; CLI R6;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8; .align 8;
[P0] = R7; [P0] = R7;
SSYNC; SSYNC;
STI R6; STI R6;
/* Configures the data cache again */ /* Configures the data cache again */
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
R7 = R7 | R6; R7 = R7 | R6;
CLI R6; CLI R6;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8; .align 8;
[P0] = R7; [P0] = R7;
SSYNC; SSYNC;
STI R6; STI R6;
( R7:6) = [SP++]; ( R7:6) = [SP++];
RTS; RTS;
ENTRY(blackfin_dcache_invalidate_range) ENTRY(blackfin_dcache_invalidate_range)
R2 = -32; R2 = -32;

1
cpu/bf533/cplbhdlr.S
View File

@ -191,4 +191,3 @@ do_not_know_what_to_do:
panic_bfin: panic_bfin:
RTS; RTS;

36
cpu/bf533/cplbmgr.S
View File

@ -52,7 +52,7 @@ ENTRY(_cplb_mgr)
/* ICPLB Miss Exception. We need to choose one of the /* ICPLB Miss Exception. We need to choose one of the
* currently-installed CPLBs, and replace it with one * currently-installed CPLBs, and replace it with one
* from the configuration table. * from the configuration table.
*/ */
P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
P4.H = (ICPLB_FAULT_ADDR >> 16); P4.H = (ICPLB_FAULT_ADDR >> 16);
@ -167,7 +167,7 @@ ie_move:P0+=4;
* addresses and page-lengths from the config table, and * addresses and page-lengths from the config table, and
* determining whether the fault address falls within that * determining whether the fault address falls within that
* range. * range.
*/ */
P2.L = ipdt_table; P2.L = ipdt_table;
P2.H = ipdt_table; P2.H = ipdt_table;
@ -201,7 +201,7 @@ inext: R4 = [P2++]; /* address from config table */
/* See if failed address > start address */ /* See if failed address > start address */
CC = R4 <= R0(IU); CC = R4 <= R0(IU);
IF !CC JUMP inext; IF !CC JUMP inext;
/* extract page size (17:16)*/ /* extract page size (17:16)*/
R3 = EXTRACT(R2, R1.L) (Z); R3 = EXTRACT(R2, R1.L) (Z);
@ -250,17 +250,17 @@ inext: R4 = [P2++]; /* address from config table */
/* FAILED CASES*/ /* FAILED CASES*/
no_page_in_table: no_page_in_table:
( R7:0,P5:0 ) = [SP++]; ( R7:0,P5:0 ) = [SP++];
R0 = CPLB_NO_ADDR_MATCH; R0 = CPLB_NO_ADDR_MATCH;
RTS; RTS;
all_locked: all_locked:
( R7:0,P5:0 ) = [SP++]; ( R7:0,P5:0 ) = [SP++];
R0 = CPLB_NO_UNLOCKED; R0 = CPLB_NO_UNLOCKED;
RTS; RTS;
prot_violation: prot_violation:
( R7:0,P5:0 ) = [SP++]; ( R7:0,P5:0 ) = [SP++];
R0 = CPLB_PROT_VIOL; R0 = CPLB_PROT_VIOL;
RTS; RTS;
dcplb_write: dcplb_write:
@ -379,7 +379,7 @@ sdsearch2:
CC = R2 == 0; /* If none are set, it'll do.*/ CC = R2 == 0; /* If none are set, it'll do.*/
IF !CC JUMP skip_stack_check; IF !CC JUMP skip_stack_check;
R2 = [P0 - 0x104]; /* R2 - PageStart */ R2 = [P0 - 0x104]; /* R2 - PageStart */
P3.L = page_size_table; /* retrive end address */ P3.L = page_size_table; /* retrive end address */
P3.H = page_size_table; /* retrive end address */ P3.H = page_size_table; /* retrive end address */
R3 = 0x2; /* 0th - position, 2 bits -length */ R3 = 0x2; /* 0th - position, 2 bits -length */
@ -392,7 +392,7 @@ sdsearch2:
R7 = R7 << 0xA; /* in bytes * 1024*/ R7 = R7 << 0xA; /* in bytes * 1024*/
R7 = R2 + R7; /* R7 - PageEnd */ R7 = R2 + R7; /* R7 - PageEnd */
R4 = SP; /* Test SP is in range */ R4 = SP; /* Test SP is in range */
CC = R7 < R4; /* if PageEnd < SP */ CC = R7 < R4; /* if PageEnd < SP */
IF CC JUMP dfound_victim; IF CC JUMP dfound_victim;
@ -450,14 +450,14 @@ dicount_done:
CC = BITTST(R1, 7); /* Is it dirty?*/ CC = BITTST(R1, 7); /* Is it dirty?*/
IF !CC JUMP Ddoverwrite (BP); /* Nope.*/ IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
CC = BITTST(R1, 14); /* Is it Write-Through?*/ CC = BITTST(R1, 14); /* Is it Write-Through?*/
IF CC JUMP Ddoverwrite; /* Yep*/ IF CC JUMP Ddoverwrite; /* Yep*/
/* This is a dirty page, so we need to flush all writes /* This is a dirty page, so we need to flush all writes
* that are pending on the page. * that are pending on the page.
*/ */
/* Retrieve the page start address*/ /* Retrieve the page start address*/
R0 = [P0 - 0x104]; R0 = [P0 - 0x104];
[--sp] = rets; [--sp] = rets;
CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/ CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
rets = [sp++]; rets = [sp++];
@ -485,7 +485,7 @@ Ddoverwrite:
ds_move: ds_move:
R0 = [P0++]; /* move data */ R0 = [P0++]; /* move data */
[P0 - 8] = R0; [P0 - 8] = R0;
R0 = [P0-0x104] /* move address */ R0 = [P0-0x104] /* move address */
de_move: [P0-0x108] = R0; de_move: [P0-0x108] = R0;
/* We've now made space in DCPLB15 for the new CPLB to be /* We've now made space in DCPLB15 for the new CPLB to be
@ -521,7 +521,7 @@ dnext: R4 = [P2++]; /* address */
/* See if failed address > start address */ /* See if failed address > start address */
CC = R4 <= R0(IU); CC = R4 <= R0(IU);
IF !CC JUMP dnext; IF !CC JUMP dnext;
/* extract page size (17:16)*/ /* extract page size (17:16)*/
R3 = EXTRACT(R2, R1.L) (Z); R3 = EXTRACT(R2, R1.L) (Z);

5
cpu/bf533/cpu.c
View File

@ -86,10 +86,6 @@ static unsigned int dcplb_table[16][2]={
{0x20000000,SDRAM_EBIU}, /*For Network */ {0x20000000,SDRAM_EBIU}, /*For Network */
}; };
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
__asm__ __volatile__ __asm__ __volatile__
@ -173,7 +169,6 @@ void dcache_enable(void)
sti(); sti();
} }
void dcache_disable(void) void dcache_disable(void)
{ {
cli(); cli();

6
cpu/bf533/serial.c
View File

@ -178,9 +178,9 @@ static void local_put_char(char ch)
save_and_cli(flags); save_and_cli(flags);
/* Poll for TX Interruput */ /* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)); while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
asm("csync;"); asm("csync;");
*pUART_THR = ch; /* putc() */ *pUART_THR = ch; /* putc() */

2
examples/stubs.c
View File

@ -131,7 +131,7 @@ gd_t *global_data;
* register * register
*/ */
#define EXPORT_FUNC(x) \ #define EXPORT_FUNC(x) \
asm volatile ( \ asm volatile ( \
" .globl " #x "\n" \ " .globl " #x "\n" \
#x ":\n" \ #x ":\n" \
" P0 = [P5 + %0]\n" \ " P0 = [P5 + %0]\n" \

100
include/configs/ezkit533.h
View File

@ -9,53 +9,53 @@
#define CONFIG_DRIVER_SMC91111 1 #define CONFIG_DRIVER_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300 #define CONFIG_SMC91111_BASE 0x20310300
#if 0 #if 0
#define CONFIG_MII #define CONFIG_MII
#define CFG_DISCOVER_PHY #define CFG_DISCOVER_PHY
#endif #endif
#define CONFIG_RTC_BF533 1 #define CONFIG_RTC_BF533 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
/* CONFIG_CLKIN_HZ is any value in Hz */ /* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 27000000 #define CONFIG_CLKIN_HZ 27000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
/* 1=CLKIN/2 */ /* 1=CLKIN/2 */
#define CONFIG_CLKIN_HALF 0 #define CONFIG_CLKIN_HALF 0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
/* 1=bypass PLL */ /* 1=bypass PLL */
#define CONFIG_PLL_BYPASS 0 #define CONFIG_PLL_BYPASS 0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
/* Values can range from 1-64 */ /* Values can range from 1-64 */
#define CONFIG_VCO_MULT 22 #define CONFIG_VCO_MULT 22
/* CONFIG_CCLK_DIV controls what the core clock divider is */ /* CONFIG_CCLK_DIV controls what the core clock divider is */
/* Values can be 1, 2, 4, or 8 ONLY */ /* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1 #define CONFIG_CCLK_DIV 1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
/* Values can range from 1-15 */ /* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5 #define CONFIG_SCLK_DIV 5
#if ( CONFIG_CLKIN_HALF == 0 ) #if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else #else
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif #endif
#if (CONFIG_PLL_BYPASS == 0) #if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else #else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif #endif
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ #define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ #define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC16M16A2TG_75 1 #define CONFIG_MEM_MT48LC16M16A2TG_75 1
#define CONFIG_LOADS_ECHO 1 #define CONFIG_LOADS_ECHO 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
@ -66,54 +66,54 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ #define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ #define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */
#define CFG_LOAD_ADDR 0x01000000 /* default load address */ #define CFG_LOAD_ADDR 0x01000000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE 0x00000000
#define CFG_MAX_RAM_SIZE 0x02000000 #define CFG_MAX_RAM_SIZE 0x02000000
#define CFG_FLASH_BASE 0x20000000 #define CFG_FLASH_BASE 0x20000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_SIZE 0x4000 #define CFG_GBL_DATA_SIZE 0x4000
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_FLASH0_BASE 0x20000000 #define CFG_FLASH0_BASE 0x20000000
#define CFG_FLASH1_BASE 0x20200000 #define CFG_FLASH1_BASE 0x20200000
#define CFG_FLASH2_BASE 0x20280000 #define CFG_FLASH2_BASE 0x20280000
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ #define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0x20020000 #define CFG_ENV_ADDR 0x20020000
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
/* JFFS Partition offset set */ /* JFFS Partition offset set */
#define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS 1 #define CFG_JFFS2_NUM_BANKS 1
/* 512k reserved for u-boot */ /* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR 11 #define CFG_JFFS2_FIRST_SECTOR 11
/* /*
* Stack sizes * Stack sizes
*/ */
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */
#define POLL_MODE 1 #define POLL_MODE 1
#define FLASH_TOT_SECT 40 #define FLASH_TOT_SECT 40
@ -123,7 +123,7 @@
/* /*
* Initialize PSD4256 registers for using I2C * Initialize PSD4256 registers for using I2C
*/ */
#define CONFIG_MISC_INIT_R #define CONFIG_MISC_INIT_R
/* /*
* I2C settings * I2C settings
@ -144,7 +144,7 @@
*pFIO_FLAG_S = PF_SDA; \ *pFIO_FLAG_S = PF_SDA; \
asm("ssync;"); \ asm("ssync;"); \
} \ } \
else { \ else { \
*pFIO_FLAG_C = PF_SDA; \ *pFIO_FLAG_C = PF_SDA; \
asm("ssync;"); \ asm("ssync;"); \
} }
@ -152,7 +152,7 @@
*pFIO_FLAG_S = PF_SCL; \ *pFIO_FLAG_S = PF_SCL; \
asm("ssync;"); \ asm("ssync;"); \
} \ } \
else { \ else { \
*pFIO_FLAG_C = PF_SCL; \ *pFIO_FLAG_C = PF_SCL; \
asm("ssync;"); \ asm("ssync;"); \
} }
@ -166,15 +166,15 @@
#define __ADSPBF533__ 1 #define __ADSPBF533__ 1
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) /* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ #define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ #define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
*/ */
#define AMGCTLVAL 0xFF #define AMGCTLVAL 0xFF
#define AMBCTL0VAL 0x7BB07BB0 #define AMBCTL0VAL 0x7BB07BB0
#define AMBCTL1VAL 0xFFC27BB0 #define AMBCTL1VAL 0xFFC27BB0
#define CONFIG_VDSP 1 #define CONFIG_VDSP 1

125
include/configs/stamp.h
View File

@ -17,7 +17,7 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
@ -40,7 +40,7 @@
#define CONFIG_RTC_BF533 1 #define CONFIG_RTC_BF533 1
/* FLASH/ETHERNET uses the same address range */ /* FLASH/ETHERNET uses the same address range */
#define SHARED_RESOURCES 1 #define SHARED_RESOURCES 1
#define CONFIG_VDSP 1 #define CONFIG_VDSP 1
@ -49,37 +49,37 @@
* *
*/ */
/* CONFIG_CLKIN_HZ is any value in Hz */ /* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 11059200 #define CONFIG_CLKIN_HZ 11059200
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
/* 1=CLKIN/2 */ /* 1=CLKIN/2 */
#define CONFIG_CLKIN_HALF 0 #define CONFIG_CLKIN_HALF 0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
/* 1=bypass PLL */ /* 1=bypass PLL */
#define CONFIG_PLL_BYPASS 0 #define CONFIG_PLL_BYPASS 0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
/* Values can range from 1-64 */ /* Values can range from 1-64 */
#define CONFIG_VCO_MULT 45 #define CONFIG_VCO_MULT 45
/* CONFIG_CCLK_DIV controls what the core clock divider is */ /* CONFIG_CCLK_DIV controls what the core clock divider is */
/* Values can be 1, 2, 4, or 8 ONLY */ /* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1 #define CONFIG_CCLK_DIV 1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
/* Values can range from 1-15 */ /* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 6 #define CONFIG_SCLK_DIV 6
/* /*
* Network Settings * Network Settings
*/ */
/* network support */ /* network support */
#define CONFIG_IPADDR 192.168.0.15 #define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.2 #define CONFIG_SERVERIP 192.168.0.2
#define CONFIG_HOSTNAME STAMP #define CONFIG_HOSTNAME STAMP
#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs #define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
/* To remove hardcoding and enable MAC storage in EEPROM */ /* To remove hardcoding and enable MAC storage in EEPROM */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
/* /*
* Command settings * Command settings
@ -90,15 +90,15 @@
#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTDELAY 5
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND "run ramboot" #define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
CFG_CMD_CACHE | \ CFG_CMD_CACHE | \
CFG_CMD_JFFS2 | \ CFG_CMD_JFFS2 | \
CFG_CMD_DATE) CFG_CMD_DATE)
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
@ -127,14 +127,14 @@
#define CONFIG_BAUDRATE 57600 #define CONFIG_BAUDRATE 57600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ #define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_LOADS_ECHO 1 #define CONFIG_LOADS_ECHO 1
@ -154,9 +154,9 @@
* *
*/ */
#define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET #define CFG_FLASH_CFI_AMD_RESET
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
@ -165,8 +165,8 @@
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_ENV_ADDR 0x20020000 #define CFG_ENV_ADDR 0x20020000
#define CFG_ENV_SIZE 0x10000 #define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
@ -176,7 +176,7 @@
#define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS 1 #define CFG_JFFS2_NUM_BANKS 1
/* 512k reserved for u-boot */ /* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR 11 #define CFG_JFFS2_FIRST_SECTOR 11
/* /*
* following timeouts shall be used once the * following timeouts shall be used once the
@ -204,7 +204,7 @@
*pFIO_FLAG_S = PF_SDA; \ *pFIO_FLAG_S = PF_SDA; \
asm("ssync;"); \ asm("ssync;"); \
} \ } \
else { \ else { \
*pFIO_FLAG_C = PF_SDA; \ *pFIO_FLAG_C = PF_SDA; \
asm("ssync;"); \ asm("ssync;"); \
} }
@ -212,7 +212,7 @@
*pFIO_FLAG_S = PF_SCL; \ *pFIO_FLAG_S = PF_SCL; \
asm("ssync;"); \ asm("ssync;"); \
} \ } \
else { \ else { \
*pFIO_FLAG_C = PF_SCL; \ *pFIO_FLAG_C = PF_SCL; \
asm("ssync;"); \ asm("ssync;"); \
} }
@ -236,9 +236,9 @@
/* /*
* IDE/ATA stuff * IDE/ATA stuff
*/ */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */ #undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */ #undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
@ -246,9 +246,9 @@
#define CFG_ATA_BASE_ADDR 0x20200000 #define CFG_ATA_BASE_ADDR 0x20200000
#define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ #define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ #define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 2 #define CFG_ATA_STRIDE 2
#endif #endif
@ -258,23 +258,20 @@
* *
*/ */
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ #define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ #define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 #define CONFIG_MEM_MT48LC64M4A2FB_7E 1
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ #define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
#define CFG_LOAD_ADDR 0x01000000 /* default load address */ #define CFG_LOAD_ADDR 0x01000000 /* default load address */
#define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE 0x00000000
#define CFG_MAX_RAM_SIZE 0x08000000 #define CFG_MAX_RAM_SIZE 0x08000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
#if ( CONFIG_CLKIN_HALF == 0 ) #if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else #else
@ -289,14 +286,12 @@
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif #endif
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CFG_HZ 1000 /* 1ms time tick */ #define CFG_HZ 1000 /* 1ms time tick */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_SIZE 0x4000 #define CFG_GBL_DATA_SIZE 0x4000
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
@ -309,25 +304,24 @@
/* /*
* Stack sizes * Stack sizes
*/ */
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */
/* /*
* FLASH organization and environment definitions * FLASH organization and environment definitions
*/ */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ /* 0xFF, 0xBBC3BBc3, 0x99B39983 */
/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) /*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ #define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ #define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
*/ */
#define AMGCTLVAL 0xFF #define AMGCTLVAL 0xFF
#define AMBCTL0VAL 0xBBC3BBC3 #define AMBCTL0VAL 0xBBC3BBC3
#define AMBCTL1VAL 0x99B39983 #define AMBCTL1VAL 0x99B39983
#define CF_AMBCTL1VAL 0x99B3ffc2 #define CF_AMBCTL1VAL 0x99B3ffc2
#ifdef CONFIG_VDSP #ifdef CONFIG_VDSP
#define ET_EXEC_VDSP 0x8 #define ET_EXEC_VDSP 0x8
@ -336,5 +330,4 @@
#define VDSP_ENTRY_ADDR 0xFFA00000 #define VDSP_ENTRY_ADDR 0xFFA00000
#endif #endif
#endif #endif

2
lib_blackfin/bf533_linux.c
View File

@ -46,7 +46,7 @@
#define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */ #define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */
#ifdef SHARED_RESOURCES #ifdef SHARED_RESOURCES
extern void swap_to(int device_id); extern void swap_to(int device_id);
#endif #endif
static char *make_command_line(void); static char *make_command_line(void);

2
lib_blackfin/board.c
View File

@ -147,7 +147,7 @@ void board_init_f(ulong bootflag)
addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t)); addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
/* Align to 4 byte boundary */ /* Align to 4 byte boundary */
addr &= ~(4 - 1); addr &= ~(4 - 1);
bd = (bd_t*)addr; bd = (bd_t*)addr;
gd->bd = bd; gd->bd = bd;
memset((void *) bd, 0, sizeof(bd_t)); memset((void *) bd, 0, sizeof(bd_t));

19
lib_blackfin/cache.c
View File

@ -26,16 +26,15 @@
*/ */
/* for now: just dummy functions to satisfy the linker */ /* for now: just dummy functions to satisfy the linker */
extern void blackfin_icache_range(unsigned long *,unsigned long *); extern void blackfin_icache_range (unsigned long *, unsigned long *);
extern void blackfin_dcache_range(unsigned long *,unsigned long *); extern void blackfin_dcache_range (unsigned long *, unsigned long *);
void flush_cache(unsigned long dummy1, unsigned long dummy2) void flush_cache (unsigned long dummy1, unsigned long dummy2)
{ {
if(icache_status()){ if (icache_status ()) {
blackfin_icache_flush_range(dummy1,dummy1+dummy2); blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
} }
if(dcache_status()){ if (dcache_status ()) {
blackfin_dcache_flush_range(dummy1,dummy1+dummy2); blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
} }
return; return;
} }

50
rtc/bf533_rtc.c
View File

@ -54,25 +54,25 @@
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/cpu/bf533_rtc.h> #include <asm/cpu/bf533_rtc.h>
void rtc_reset(void) void rtc_reset (void)
{ {
return; /* nothing to do */ return; /* nothing to do */
} }
/* Wait for pending writes to complete */ /* Wait for pending writes to complete */
void wait_for_complete(void) void wait_for_complete (void)
{ {
while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) { while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
printf(""); printf ("");
} }
*(volatile unsigned short *) RTC_ISTAT = 0x8000; *(volatile unsigned short *) RTC_ISTAT = 0x8000;
} }
/* Enable the RTC prescaler enable register */ /* Enable the RTC prescaler enable register */
void rtc_init() void rtc_init ()
{ {
*(volatile unsigned short *) RTC_PREN = 0x1; *(volatile unsigned short *) RTC_PREN = 0x1;
wait_for_complete(); wait_for_complete ();
} }
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers /* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
@ -81,25 +81,27 @@ void rtc_init()
void rtc_set (struct rtc_time *tmp) void rtc_set (struct rtc_time *tmp)
{ {
unsigned long n_days_1970 = 0; unsigned long n_days_1970 = 0;
unsigned long n_secs_rem = 0; unsigned long n_secs_rem = 0;
unsigned long n_hrs = 0; unsigned long n_hrs = 0;
unsigned long n_mins = 0; unsigned long n_mins = 0;
unsigned long n_secs = 0; unsigned long n_secs = 0;
unsigned long time_in_secs; unsigned long time_in_secs;
if(tmp == NULL) { if (tmp == NULL) {
printf("Error setting the date/time \n"); printf ("Error setting the date/time \n");
return; return;
} }
time_in_secs = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,tmp->tm_hour, tmp->tm_min, tmp->tm_sec); time_in_secs =
mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
tmp->tm_min, tmp->tm_sec);
/* Compute no. of days since 1970 */ /* Compute no. of days since 1970 */
n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY)); n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
/* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY)); n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY));
n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR); n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR); n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
n_mins = n_secs_rem / (NUM_SECS_IN_MIN); n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
n_secs = n_secs_rem % (NUM_SECS_IN_MIN); n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
@ -107,9 +109,9 @@ void rtc_set (struct rtc_time *tmp)
/* Store the new time in the RTC_STAT register */ /* Store the new time in the RTC_STAT register */
*(volatile unsigned long *) RTC_STAT = *(volatile unsigned long *) RTC_STAT =
((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) | ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
(n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF)); (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
wait_for_complete(); wait_for_complete ();
} }
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ /* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
@ -119,8 +121,8 @@ void rtc_get (struct rtc_time *tmp)
unsigned long time_in_sec; unsigned long time_in_sec;
unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
if(tmp == NULL) { if (tmp == NULL) {
printf("Error getting the date/time \n"); printf ("Error getting the date/time \n");
return; return;
} }
@ -134,10 +136,10 @@ void rtc_get (struct rtc_time *tmp)
tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff; tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
/* Calculate the total number of seconds since Jan 1970 */ /* Calculate the total number of seconds since Jan 1970 */
time_in_sec = (tm_sec) + time_in_sec = (tm_sec) +
MIN_TO_SECS(tm_min) + MIN_TO_SECS (tm_min) +
HRS_TO_SECS(tm_hour) + HRS_TO_SECS (tm_hour) +
DAYS_TO_SECS(tm_day); DAYS_TO_SECS (tm_day);
to_tm(time_in_sec,tmp); to_tm (time_in_sec, tmp);
} }
#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */ #endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */