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ADD: added hw17 platform and cleaned up naming of nm boards 

BugzId: 70910
This commit is contained in:
Marcel Reichmuth 2021-03-30 14:08:51 +02:00
parent 1ffa09d30f
commit 8efea863e6
33 changed files with 212 additions and 199 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
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@ -84,8 +84,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ARCH_MVEBU) += \ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-385-hw14.dtb \ armada-385-hw14.dtb \
armada-385-nbhw18-v2.dtb \ armada-385-hw18.dtb \
armada-385-nbhw17-v1.dtb \ armada-385-hw17.dtb \
armada-3720-db.dtb \ armada-3720-db.dtb \
armada-3720-espressobin.dtb \ armada-3720-espressobin.dtb \
armada-375-db.dtb \ armada-375-db.dtb \

2
arch/arm/dts/armada-385-hw14.dts
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@ -1,5 +1,5 @@
/* /*
* Device Tree file for the NetModule NBHW18-V2 (NB1800) base variant * Device Tree file for the NetModule HW14 (NB1800) base variant
* *
* Copyright (C) 2016 NetModule * Copyright (C) 2016 NetModule
* *

7
arch/arm/dts/armada-385-nbhw17-common.dtsi → arch/arm/dts/armada-385-hw17-common.dtsi
View File

@ -44,6 +44,13 @@
rst_fpga = <&gpio1 12 GPIO_ACTIVE_LOW 1>; rst_fpga = <&gpio1 12 GPIO_ACTIVE_LOW 1>;
rst_eth_phy = <&gpio0 21 GPIO_ACTIVE_LOW 1>; rst_eth_phy = <&gpio0 21 GPIO_ACTIVE_LOW 1>;
reset_button = <&gpio1 24 GPIO_ACTIVE_LOW 1>; reset_button = <&gpio1 24 GPIO_ACTIVE_LOW 1>;
gps_ant_pwr_en = <&gpiofpga 65 GPIO_ACTIVE_HIGH 0>;
mdio_phy_con = <&gpiofpga 66 GPIO_ACTIVE_LOW 0>;
mdio_ext_con = <&gpiofpga 67 GPIO_ACTIVE_LOW 0>;
sata_pwr_en = <&gpiofpga 68 GPIO_ACTIVE_HIGH 0>;
serdes_sel_pci = <&gpiofpga 69 GPIO_ACTIVE_HIGH 0>;
serdes_en = <&gpiofpga 70 GPIO_ACTIVE_LOW 1>;
rst_ext = <&gpiofpga 71 GPIO_ACTIVE_LOW 1>;
}; };
gpiofpga: gpio@fd0000000 { gpiofpga: gpio@fd0000000 {

2
arch/arm/dts/armada-385-nbhw17-v1-spl.dts → arch/arm/dts/armada-385-hw17-spl.dts
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@ -11,7 +11,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "armada-385-nbhw17-common.dtsi" #include "armada-385-hw17-common.dtsi"
/ { / {
model = "NetModule Router NBHW17 with Armada A385 (NB2800)"; model = "NetModule Router NBHW17 with Armada A385 (NB2800)";

2
arch/arm/dts/armada-385-nbhw17-v1.dts → arch/arm/dts/armada-385-hw17.dts
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@ -11,7 +11,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "armada-385-nbhw17-common.dtsi" #include "armada-385-hw17-common.dtsi"
/ { / {
model = "NetModule Router NBHW17 with Armada A385 (NB2800)"; model = "NetModule Router NBHW17 with Armada A385 (NB2800)";

0
arch/arm/dts/armada-385-nbhw18-common.dtsi → arch/arm/dts/armada-385-hw18-common.dtsi
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2
arch/arm/dts/armada-385-nbhw18-spl.dts → arch/arm/dts/armada-385-hw18-spl.dts
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@ -11,7 +11,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "armada-385-nbhw18-common.dtsi" #include "armada-385-hw18-common.dtsi"
/ { / {
model = "NetModule Router NBHW18 with Armada A385 (NB1800)"; model = "NetModule Router NBHW18 with Armada A385 (NB1800)";

8
arch/arm/dts/armada-385-nbhw18-v2.dts → arch/arm/dts/armada-385-hw18.dts
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@ -1,5 +1,5 @@
/* /*
* Device Tree file for the NetModule NBHW18-V2 (NB1800) base variant * Device Tree file for the NetModule HW18 (NB1800) base variant
* *
* Copyright (C) 2016 NetModule * Copyright (C) 2016 NetModule
* *
@ -11,15 +11,15 @@
*/ */
/dts-v1/; /dts-v1/;
#include "armada-385-nbhw18-common.dtsi" #include "armada-385-hw18-common.dtsi"
/ { / {
model = "NetModule Router NBHW18 with Armada A385 (NB1800)"; model = "NetModule Router NBHW18 with Armada A385 (NB1800)";
soc { soc {
gpiofpga: gpio@fd0000000 { gpiofpga: gpio@fd0000000 {
fpga-cinit = <&gpio0 13 0>; /* FPGA cinit HW V2 */ fpga-cinit = <&gpio0 13 0>; /* FPGA cinit */
fpga-cdone = <&gpio0 21 0>; /* FPGA cdone HW V2 */ fpga-cdone = <&gpio0 21 0>; /* FPGA cdone */
}; };
}; };
}; };

22
arch/arm/mach-mvebu/Kconfig
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@ -92,12 +92,12 @@ config TARGET_NM_HW14
bool "Support HW14" bool "Support HW14"
select 88F6820 select 88F6820
config TARGET_NM_NBHW18_V2 config TARGET_NM_HW18
bool "Support NBHW18 V2" bool "Support HW18"
select 88F6820 select 88F6820
config TARGET_NM_NBHW17_V1 config TARGET_NM_HW17
bool "Support NBHW17 V1" bool "Support HW17"
select 88F6820 select 88F6820
config TARGET_TURRIS_OMNIA config TARGET_TURRIS_OMNIA
@ -155,9 +155,8 @@ config SYS_BOARD
default "maxbcm" if TARGET_MAXBCM default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE default "theadorable" if TARGET_THEADORABLE
default "hw14" if TARGET_NM_HW14 default "hw14" if TARGET_NM_HW14
default "nbhw18_v1" if TARGET_NM_NBHW18_V1 default "hw18" if TARGET_NM_HW18
default "nbhw18_v2" if TARGET_NM_NBHW18_V2 default "hw17" if TARGET_NM_HW17
default "nbhw17_v1" if TARGET_NM_NBHW17_V1
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG default "clearfog" if TARGET_CLEARFOG
@ -172,8 +171,8 @@ config SYS_CONFIG_NAME
default "theadorable" if TARGET_THEADORABLE default "theadorable" if TARGET_THEADORABLE
default "turris_omnia" if TARGET_TURRIS_OMNIA default "turris_omnia" if TARGET_TURRIS_OMNIA
default "armada-385-hw14" if TARGET_NM_HW14 default "armada-385-hw14" if TARGET_NM_HW14
default "armada-385-nbhw18-v2" if TARGET_NM_NBHW18_V2 default "armada-385-hw18" if TARGET_NM_HW18
default "armada-385-nbhw17-v1" if TARGET_NM_NBHW17_V1 default "armada-385-hw17" if TARGET_NM_HW17
config SYS_VENDOR config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP default "Marvell" if TARGET_DB_MV784MP_GP
@ -186,9 +185,8 @@ config SYS_VENDOR
default "Synology" if TARGET_DS414 default "Synology" if TARGET_DS414
default "CZ.NIC" if TARGET_TURRIS_OMNIA default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "nm" if TARGET_NM_HW14 default "nm" if TARGET_NM_HW14
default "nm" if TARGET_NM_NBHW18_V1 default "nm" if TARGET_NM_HW18
default "nm" if TARGET_NM_NBHW18_V2 default "nm" if TARGET_NM_HW17
default "nm" if TARGET_NM_NBHW17_V1
config SYS_SOC config SYS_SOC
default "mvebu" default "mvebu"

0
board/nm/nbhw17_v1/MAINTAINERS → board/nm/hw17/MAINTAINERS
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2
board/nm/nbhw17_v1/Makefile → board/nm/hw17/Makefile
View File

@ -17,6 +17,7 @@ ccflags-y := -I../common
ifndef CONFIG_SPL_BUILD ifndef CONFIG_SPL_BUILD
obj-y := board.o nbhw_gpio.o nbhw_fpga_config.o \ obj-y := board.o nbhw_gpio.o nbhw_fpga_config.o \
../common/nbhw_sim.o nbhw_sim.o \
$(commonobj) $(commonobj)
else else
obj-y := board.o \ obj-y := board.o \
@ -26,4 +27,3 @@ obj-y := board.o \
../common/nbhw_bd.o ../common/nbhw_bd.o
endif endif

0
board/nm/nbhw17_v1/README → board/nm/hw17/README
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64
board/nm/nbhw17_v1/board.c → board/nm/hw17/board.c
View File

@ -27,6 +27,7 @@
#include "../common/nbhw_init.h" #include "../common/nbhw_init.h"
#include "../common/nbhw_env.h" #include "../common/nbhw_env.h"
#include "../common/nbhw_bd.h" #include "../common/nbhw_bd.h"
#include "../common/nbhw_fpga_prog.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h> #include <../serdes/a38x/high_speed_env_spec.h>
@ -40,11 +41,11 @@ DECLARE_GLOBAL_DATA_PTR;
* "u-boot-2013.01-2014_T3.0" * "u-boot-2013.01-2014_T3.0"
*/ */
/* 21: RST_ETH_PHYS~, 26: FPGA_CFG_RESET, 27: WD_ENABLE~ */ /* 21: RST_ETH_PHYS~, 26: FPGA_CFG_RESET, 27: WD_ENABLE~ */
#define GPP_OUT_ENA_LOW (~(BIT(21) | BIT(26) /*| BIT(27) */)) /* 1=Input, default input */ #define GPP_OUT_ENA_LOW (~(BIT(21) | BIT(26) | BIT(27))) /* 1=Input, default input */
/* 41/9: RST_USB_HUB~, 44/12: RST_FPGA~, 47/15: WD_TRIG */ /* 41/9: RST_USB_HUB~, 44/12: RST_FPGA~, 47/15: WD_TRIG */
#define GPP_OUT_ENA_MID (~(BIT(9) | BIT(12) | BIT(15))) #define GPP_OUT_ENA_MID (~(BIT(9) | BIT(12) | BIT(15)))
#define GPP_OUT_VAL_LOW (BIT(21)) /* 1=pin on */ #define GPP_OUT_VAL_LOW (BIT(21) | BIT(27)) /* 1=pin on */
#define GPP_OUT_VAL_MID (0x0) #define GPP_OUT_VAL_MID (0x0)
#define GPP_POL_LOW (0x0) /* 0=no inversion */ #define GPP_POL_LOW (0x0) /* 0=no inversion */
#define GPP_POL_MID (0x0) #define GPP_POL_MID (0x0)
@ -57,24 +58,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define DEV_CS0_BASE 0xfd000000 #define DEV_CS0_BASE 0xfd000000
/* Chip select base addresses */
#define NBHW_BASE_ADDRESS_FPGA DEV_CS0_BASE
/* Compute FPGA register addresses */
#define FPGA_REG(x) *((volatile unsigned short*)( NBHW_BASE_ADDRESS_FPGA + ((unsigned int)x)))
#define PCIE_4_PCM_GPIO_EN (0x0430) #define PCIE_4_PCM_GPIO_EN (0x0430)
#define PCIE_4_PCM_GPIO_DIR (0x0432) #define PCIE_4_PCM_GPIO_DIR (0x0432)
#define PCIE_4_PCM_GPIO_DAT (0x0434) #define PCIE_4_PCM_GPIO_DAT (0x0434)
/* TODO: These platform specific SERDES default definitions are /* Default serdes configuration */
currently defined twice here and in by hws_board_topology_load().
Actually these platform specific defaults should only be set
in hws_board_topology_load().
The defaults should there be set also for the case where we have
a valid BD but that BD does not contain SERDES configuration
info to support old HW14 boards.
*/
static struct serdes_map board_serdes_map[] = { static struct serdes_map board_serdes_map[] = {
{ PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0 }, { PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0 },
{ SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0 }, { SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0 },
@ -240,31 +228,9 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
int i; int i;
if (read_eeprom() < 0){ if (read_eeprom() < 0){
/* If we do not have a board descriptor use the default
serdes configuration defined in board_serdes_map */
puts("Could not read board descriptor using default serdes config.\n"); puts("Could not read board descriptor using default serdes config.\n");
board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
board_serdes_map[0].serdes_type = PEX0;
board_serdes_map[1].serdes_speed = SERDES_SPEED_1_25_GBPS;
board_serdes_map[1].serdes_mode = SERDES_DEFAULT_MODE;
board_serdes_map[1].serdes_type = SGMII1;
board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
board_serdes_map[2].serdes_type = SATA1;
board_serdes_map[3].serdes_speed = SERDES_SPEED_1_25_GBPS;
board_serdes_map[3].serdes_mode = SERDES_DEFAULT_MODE;
board_serdes_map[3].serdes_type = SGMII2;
board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
board_serdes_map[4].serdes_mode = PEX_ROOT_COMPLEX_X1;
board_serdes_map[4].serdes_type = PEX2;
board_serdes_map[5].serdes_speed = SERDES_SPEED_5_GBPS;
board_serdes_map[5].serdes_mode = SERDES_DEFAULT_MODE;
board_serdes_map[5].serdes_type = USB3_HOST1;
} else { } else {
for (i = 0; i < ARRAY_SIZE(board_serdes_map); i++) { for (i = 0; i < ARRAY_SIZE(board_serdes_map); i++) {
enum serdes_type type; enum serdes_type type;
@ -530,12 +496,17 @@ static int check_reset_button(void)
set_led(LED3_GREEN, 1); set_led(LED3_GREEN, 1);
set_led(LED4_GREEN, 1); set_led(LED4_GREEN, 1);
set_led(LED5_GREEN, 1); set_led(LED5_GREEN, 1);
set_led(LED6_GREEN, 1);
set_led(LED7_GREEN, 1);
udelay(400000); /* 400ms */ udelay(400000); /* 400ms */
set_led(LED1_GREEN, 0); set_led(LED1_GREEN, 0);
set_led(LED2_GREEN, 0); set_led(LED2_GREEN, 0);
set_led(LED3_GREEN, 0); set_led(LED3_GREEN, 0);
set_led(LED4_GREEN, 0); set_led(LED4_GREEN, 0);
set_led(LED5_GREEN, 0); set_led(LED5_GREEN, 0);
set_led(LED6_GREEN, 0);
set_led(LED7_GREEN, 0);
} else if (counter == 12000) { } else if (counter == 12000) {
/* Indicate recovery boot threshold */ /* Indicate recovery boot threshold */
@ -547,6 +518,8 @@ static int check_reset_button(void)
set_led(LED3_RED, 1); set_led(LED3_RED, 1);
set_led(LED4_RED, 1); set_led(LED4_RED, 1);
set_led(LED5_RED, 1); set_led(LED5_RED, 1);
set_led(LED6_RED, 1);
set_led(LED7_RED, 1);
udelay(400000); /* 400ms */ udelay(400000); /* 400ms */
set_led(LED0_RED, 0); set_led(LED0_RED, 0);
set_led(LED1_RED, 0); set_led(LED1_RED, 0);
@ -554,6 +527,8 @@ static int check_reset_button(void)
set_led(LED3_RED, 0); set_led(LED3_RED, 0);
set_led(LED4_RED, 0); set_led(LED4_RED, 0);
set_led(LED5_RED, 0); set_led(LED5_RED, 0);
set_led(LED6_RED, 0);
set_led(LED7_RED, 0);
set_led(LED0_GREEN, 1); set_led(LED0_GREEN, 1);
} }
} while (counter < 12000); } while (counter < 12000);
@ -633,7 +608,7 @@ int misc_init_r(void)
/* Disable watchdog */ /* Disable watchdog */
debug("Disable watchdog\n"); debug("Disable watchdog\n");
// set_gpio(GPIO_WD_ENABLE, 0); set_gpio(GPIO_WD_ENABLE, 0);
/* Enable USB hub */ /* Enable USB hub */
debug("Enable USB Hub\n"); debug("Enable USB Hub\n");
@ -702,7 +677,8 @@ int board_late_init(void)
check_reset_button(); check_reset_button();
set_mac_addresses(2); set_mac_address(1,0);
set_mac_address(2,1);
#endif #endif
/* Take phy out of reset after FPGA was loaded */ /* Take phy out of reset after FPGA was loaded */
@ -747,11 +723,11 @@ int board_fit_config_name_match(const char *name)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
/* SPL has enabled serial1 per default and will output everything /* SPL has enabled serial1 per default and will output everything
* independend of /boot/consoledev */ * independend of /boot/consoledev */
#define DEFAULT_DTB_NAME "armada-385-nbhw17-v1-spl" #define DEFAULT_DTB_NAME "armada-385-hw17-spl"
#else #else
/* U-Boot will read /boot/consoledev and based on that it /* U-Boot will read /boot/consoledev and based on that it
* enables its own serial console */ * enables its own serial console */
#define DEFAULT_DTB_NAME "armada-385-nbhw17-v1" #define DEFAULT_DTB_NAME "armada-385-hw17"
#endif #endif
/* Check if name fits our dts */ /* Check if name fits our dts */

0
board/nm/nbhw17_v1/kwbimage.cfg → board/nm/hw17/kwbimage.cfg
View File

182
board/nm/nbhw17_v1/nbhw_fpga_config.c → board/nm/hw17/nbhw_fpga_config.c
View File

@ -7,9 +7,18 @@
#include <asm/io.h> #include <asm/io.h>
#include <errno.h> #include <errno.h>
#include "../common/nbhw_bd.h" #include "../common/nbhw_bd.h"
#include "../common/nbhw_sim.h"
#include "../common/nbhw_fpga_prog.h"
#include "nbhw_gpio.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define PCIE_SIM_CLOCK (0x0034)
#define INTMASK1 (0x0010)
#define INTMASK2 (0x0012)
#define INTACK1 (0x0018)
#define INTACK2 (0x001A)
struct gpio_desc leds[16]; struct gpio_desc leds[16];
struct udevice *driver_dev; struct udevice *driver_dev;
@ -31,54 +40,6 @@ typedef enum {
TYPE_PCIE, TYPE_PCIE,
} slot_type_t; } slot_type_t;
//static slot_type_t get_pcie_slot_type(const int slot)
//{
// int module;
// char pdValue[200];
// char slotDescr[20];
//
// sprintf(slotDescr, "slot=%d", slot);
//
// for (module=0; module<4; module++) {
// strcpy(pdValue, "" ); /*init with an empty string*/
// if (bd_get_pd_module(module, pdValue, sizeof(pdValue))==0) {
//
// if ((strstr(pdValue, slotDescr)) && (strstr(pdValue, "wlan-"))) {
// /* Wifi module needs PCIe */
// return TYPE_PCIE;
// }
// }
// }
//
// return TYPE_USB;
//}
//
//static int serdes_en_hack(struct gpio_desc *gpio)
//{
// slot_type_t slot_type = get_pcie_slot_type(0);
//
// /* Lucky for us pcie slot1 has some muxes, to workaround buggy Sierra Wireless Modules */
// if (slot_type == TYPE_USB) {
// /* Buggy Sierra Wireless Modules don't like to have USB3 enabled
// * because the TX of the USB3 Lane is attached to it's system
// * reset which is the default (see dts) */
// printf("Slot1: wwan\n");
// }
// else if (slot_type == TYPE_PCIE) {
// dm_gpio_set_value(gpio, 1);
// printf("Slot1: wlan\n");
// }
// else {
// /* If once we would use other buggy Sierra Wireless modules, where they have
// * decided to use USB3 too, then we have to enable the SERDES, the reset signal
// * was moved away from this pins again (bravo!!!) */
// printf("Slot1: wwan (usb3)\n");
// }
//
// return 0;
//
//}
struct pcie_slot_gpios { struct pcie_slot_gpios {
struct gpio_desc reset; struct gpio_desc reset;
struct gpio_desc power; struct gpio_desc power;
@ -139,10 +100,71 @@ static int add_pcie_slot(ofnode fdt)
return 0; return 0;
} }
static slot_type_t get_pcie_slot_type(const int slot)
{
int module;
char pdValue[200];
char slotDescr[20];
sprintf(slotDescr, "slot=%d", slot);
for (module=0; module<4; module++) {
strcpy(pdValue, "" ); /*init with an empty string*/
if (bd_get_pd_module(module, pdValue, sizeof(pdValue))==0) {
if ((strstr(pdValue, slotDescr)) && (strstr(pdValue, "wlan-"))) {
/* Wifi module needs PCIe */
return TYPE_PCIE;
}
}
}
return TYPE_USB;
}
static void configure_pcie_muxes(void)
{
slot_type_t slot_type = get_pcie_slot_type(0);
/* Lucky for us pcie slot1 has some muxes, to workaround buggy Sierra Wireless Modules */
if (slot_type == TYPE_USB) {
/* Buggy Sierra Wireless Modules don't like to have USB3 enabled
* because the TX of the USB3 Lane is attached to it's system
* reset which is the default (see dts) -> This obviously means
* that slot1 will never do USB3 even if it was capable. */
set_gpio(GPIO_SERDES_SEL_PCI, 0);
set_gpio(GPIO_SERDES_EN, 0);
printf("Slot1: wwan\n");
}
else if (slot_type == TYPE_PCIE) {
set_gpio(GPIO_SERDES_SEL_PCI, 1);
set_gpio(GPIO_SERDES_EN, 1);
printf("Slot1: wlan\n");
}
else {
/* If once we would use other buggy Sierra Wireless modules, where they have
* decided to use USB3 too, then we have to enable the SERDES, the reset signal
* was moved away from this pins again (bravo!!!)
* Note: We currently never get here. */
printf("Slot1: wwan (usb3)\n");
set_gpio(GPIO_SERDES_SEL_PCI, 0);
set_gpio(GPIO_SERDES_EN, 1);
}
}
static int configure_pcie_slots(void) static int configure_pcie_slots(void)
{ {
int i; int i;
configure_pcie_muxes();
configure_sim_slots(4);
/* Disable power for all PCIe slots */
for (i = 0; i < pcie_slot_count; i++) {
dm_gpio_set_value(&pcie_slots[i].power, 0);
}
udelay(1200000); /* 1.2 s */ udelay(1200000); /* 1.2 s */
/* Apply power to all PCIe slots */ /* Apply power to all PCIe slots */
@ -151,11 +173,6 @@ static int configure_pcie_slots(void)
udelay(200000); /* 200 ms */ udelay(200000); /* 200 ms */
} }
/* Assert reset after power is enabled */
for (i = 0; i < pcie_slot_count; i++) {
dm_gpio_set_value(&pcie_slots[i].reset, 1);
}
/* Deactivate WDIS */ /* Deactivate WDIS */
for (i = 0; i < pcie_slot_count; i++) { for (i = 0; i < pcie_slot_count; i++) {
dm_gpio_set_value(&pcie_slots[i].wdis_out, 1); dm_gpio_set_value(&pcie_slots[i].wdis_out, 1);
@ -163,6 +180,11 @@ static int configure_pcie_slots(void)
udelay(2000); /* 2 ms needed by Reyax module as regulator is enabled by WDIS~*/ udelay(2000); /* 2 ms needed by Reyax module as regulator is enabled by WDIS~*/
} }
/* Assert reset after power is enabled */
for (i = 0; i < pcie_slot_count; i++) {
dm_gpio_set_value(&pcie_slots[i].reset, 1);
}
udelay(12000); /* 12 ms */ udelay(12000); /* 12 ms */
/* Deassert reset */ /* Deassert reset */
@ -192,33 +214,7 @@ static int configure_leds(void)
return 0; return 0;
} }
// TODO: Check, if needed
//struct hack_list_entry {
// const char* name;
// int (*fn)(struct gpio_desc *gpio);
//};
//
//struct hack_list_entry hack_list[] = {
// {"serdes-en", serdes_en_hack}
//};
//
//static int exec_hack_list_fn(const char *name, struct gpio_desc *gpio)
//{
// int i;
// for (i = 0; i < ARRAY_SIZE(hack_list); i++) {
// if (strcmp(hack_list[i]. name, name) == 0) {
// if (hack_list[i].fn(gpio)) {
// printf("Hack for %s failed\n", name);
// return -1;
// }
// return 0;
// }
// }
//
// /* Not part of hacklist */
// return 0;
//}
//
void set_led(int index, int value) void set_led(int index, int value)
{ {
if ((index<0) || (index>=priv.led_count)) return; if ((index<0) || (index>=priv.led_count)) return;
@ -232,6 +228,17 @@ int nbhw_fpga_configure(void)
ofnode node = driver_dev->node; ofnode node = driver_dev->node;
debug("%s\n", __func__); debug("%s\n", __func__);
/* Disable all interrupts from FPGA and clear flags */
FPGA_REG(INTMASK1) = 0xFFFF;
FPGA_REG(INTMASK2) = 0xFFFF;
/* Make sure all interrupts are received */
udelay(10000);
FPGA_REG(INTACK1) = 0xFFFF;
FPGA_REG(INTACK2) = 0xFFFF;
/* Enable SIM clocks */
FPGA_REG(PCIE_SIM_CLOCK) = 0;
ofnode_for_each_subnode(subnode, node) { ofnode_for_each_subnode(subnode, node) {
const char *name; const char *name;
@ -244,6 +251,21 @@ int nbhw_fpga_configure(void)
} }
} }
/* Disengage extension connector reset */
set_gpio(GPIO_RST_EXT, 0);
/* Enable mdio connection to on board phy */
set_gpio(GPIO_MDIO_PHY_CON, 1);
/* Enable mdio connection to external phy */
set_gpio(GPIO_MDIO_EXT_CON, 1);
/* Enable SATA power */
set_gpio(GPIO_SATA_PWR_EN, 1);
/* Enable GPS antenna power */
set_gpio(GPIO_GPS_ANT_PWR_EN,1);
if (configure_leds()) if (configure_leds())
return -1; return -1;

0
board/nm/nbhw17_v1/nbhw_gpio.c → board/nm/hw17/nbhw_gpio.c
View File

41
board/nm/hw17/nbhw_gpio.h Normal file
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@ -0,0 +1,41 @@
#ifndef HW17_GPIO_H
#define HW17_GPIO_H
/* GPIO definitions */
#define GPIO_WD_ENABLE "wd_enable"
#define GPIO_RST_USB_HUB "rst_usb_hub"
#define GPIO_RST_FPGA "rst_fpga"
#define GPIO_RST_ETH_PHY "rst_eth_phy"
#define GPIO_RESET_BUTTON "reset_button"
#define GPIO_GPS_ANT_PWR_EN "gps_ant_pwr_en"
#define GPIO_MDIO_PHY_CON "mdio_phy_con"
#define GPIO_MDIO_EXT_CON "mdio_ext_con"
#define GPIO_SATA_PWR_EN "sata_pwr_en"
#define GPIO_SERDES_SEL_PCI "serdes_sel_pci"
#define GPIO_SERDES_EN "serdes_en"
#define GPIO_RST_EXT "rst_ext"
int get_gpio(const char* gpio_name);
int set_gpio(const char* gpio_name, int value);
/* LED definitions */
#define LED0_GREEN 0
#define LED0_RED 1
#define LED1_GREEN 2
#define LED1_RED 3
#define LED2_GREEN 4
#define LED2_RED 5
#define LED3_GREEN 6
#define LED3_RED 7
#define LED4_GREEN 8
#define LED4_RED 9
#define LED5_GREEN 10
#define LED5_RED 11
#define LED6_GREEN 12
#define LED6_RED 13
#define LED7_GREEN 14
#define LED7_RED 15
void set_led(int index, int value);
#endif

5
board/nm/nbhw17_v1/nbhw_sim.c → board/nm/hw17/nbhw_sim.c
View File

@ -1,7 +1,7 @@
#include <common.h> #include <common.h>
#include <nbhw.h> #include "../common/nbhw_fpga_prog.h"
#include "nbhw18_fpga_regs.h" #define SIM_CTRL (0x0040)
void connect_sim_to_slot(int sim, int slot) { void connect_sim_to_slot(int sim, int slot) {
uint16_t sim_ctrl; uint16_t sim_ctrl;
@ -32,4 +32,3 @@ void connect_sim_to_slot(int sim, int slot) {
FPGA_REG(SIM_CTRL) = sim_ctrl; FPGA_REG(SIM_CTRL) = sim_ctrl;
} }

0
board/nm/nbhw18_v2/MAINTAINERS → board/nm/hw18/MAINTAINERS
View File

0
board/nm/nbhw18_v2/Makefile → board/nm/hw18/Makefile
View File

0
board/nm/nbhw18_v2/README → board/nm/hw18/README
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2
board/nm/nbhw18_v2/board.c → board/nm/hw18/board.c
View File

@ -713,7 +713,7 @@ int board_fit_config_name_match(const char *name)
#else #else
/* U-Boot will read /boot/consoledev and based on that it /* U-Boot will read /boot/consoledev and based on that it
* enables its own serial console */ * enables its own serial console */
#define DEFAULT_DTB_NAME "armada-385-nbhw18-v2" #define DEFAULT_DTB_NAME "armada-385-hw18"
#endif #endif
/* Check if name fits our dts */ /* Check if name fits our dts */

0
board/nm/nbhw18_v2/kwbimage.cfg → board/nm/hw18/kwbimage.cfg
View File

0
board/nm/nbhw18_v2/nbhw_fpga_config.c → board/nm/hw18/nbhw_fpga_config.c
View File

0
board/nm/nbhw18_v2/nbhw_gpio.c → board/nm/hw18/nbhw_gpio.c
View File

0
board/nm/nbhw18_v2/nbhw_gpio.h → board/nm/hw18/nbhw_gpio.h
View File

2
board/nm/nbhw18_v2/nbhw_mvswitch.c → board/nm/hw18/nbhw_mvswitch.c
View File

@ -29,7 +29,7 @@
#define MVSWITCH_GLOBAL2_REG_DATA (0x19) #define MVSWITCH_GLOBAL2_REG_DATA (0x19)
/* Temporary FPGA defines -> To be replaced by proper definitions /* Temporary FPGA defines -> To be replaced by proper definitions
as soon as we have the register definition for NBHW18 V2 as soon as we have the register definition for HW18
*/ */
//#define OUTPUT1 (0x0008) //#define OUTPUT1 (0x0008)

0
board/nm/nbhw18_v2/nbhw_sim.c → board/nm/hw18/nbhw_sim.c
View File

30
board/nm/nbhw17_v1/nbhw_gpio.h
View File

@ -1,30 +0,0 @@
#ifndef HW17_GPIO_H
#define HW17_GPIO_H
/* GPIO definitions */
#define GPIO_WD_ENABLE "wd_enable"
#define GPIO_RST_USB_HUB "rst_usb_hub"
#define GPIO_RST_FPGA "rst_fpga"
#define GPIO_RST_ETH_PHY "rst_eth_phy"
#define GPIO_RESET_BUTTON "reset_button"
int get_gpio(const char* gpio_name);
int set_gpio(const char* gpio_name, int value);
/* LED definitions */
#define LED0_GREEN 0
#define LED0_RED 1
#define LED1_GREEN 2
#define LED1_RED 3
#define LED2_GREEN 4
#define LED2_RED 5
#define LED3_GREEN 6
#define LED3_RED 7
#define LED4_GREEN 8
#define LED4_RED 9
#define LED5_GREEN 10
#define LED5_RED 11
void set_led(int index, int value);
#endif

8
configs/armada-385-nbhw17-v1_defconfig → configs/armada-385-hw17_defconfig
View File

@ -3,11 +3,11 @@ CONFIG_ARCH_MVEBU=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_NM_NBHW17_V1=y CONFIG_TARGET_NM_HW17=y
CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-nbhw17-v1-spl" CONFIG_DEFAULT_DEVICE_TREE="armada-385-hw17-spl"
CONFIG_SMBIOS_PRODUCT_NAME="hw17" CONFIG_SMBIOS_PRODUCT_NAME="hw17"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_ENABLE_SHA256_SUPPORT=y CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
@ -18,7 +18,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_PRE_CON_BUF_SZ=4096 CONFIG_PRE_CON_BUF_SZ=4096
CONFIG_PRE_CON_BUF_ADDR=0x04000000 CONFIG_PRE_CON_BUF_ADDR=0x04000000
# CONFIG_CONSOLE_MUX is not set # CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_FDT_FILE="armada-385-nbhw17-v1-spl" CONFIG_DEFAULT_FDT_FILE="armada-385-hw17-spl"
# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x190 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x190
@ -50,7 +50,7 @@ CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_BOARD_FIXUP=y CONFIG_OF_BOARD_FIXUP=y
CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPL_OF_TRANSLATE=y
CONFIG_OF_LIST="armada-385-nbhw17-v1-spl armada-385-nbhw17-v1" CONFIG_OF_LIST="armada-385-hw17-spl armada-385-hw17"
CONFIG_MULTI_DTB_FIT=y CONFIG_MULTI_DTB_FIT=y
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y

10
configs/armada-385-nbhw18-v2_defconfig → configs/armada-385-hw18_defconfig
View File

@ -3,12 +3,12 @@ CONFIG_ARCH_MVEBU=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_NM_NBHW18_V2=y CONFIG_TARGET_NM_HW18=y
CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-nbhw18-spl" CONFIG_DEFAULT_DEVICE_TREE="armada-385-hw18-spl"
CONFIG_SMBIOS_PRODUCT_NAME="nbhw18_v2" CONFIG_SMBIOS_PRODUCT_NAME="hw18"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_ENABLE_SHA256_SUPPORT=y CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
CONFIG_BOOTDELAY=3 CONFIG_BOOTDELAY=3
@ -18,7 +18,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_PRE_CON_BUF_SZ=4096 CONFIG_PRE_CON_BUF_SZ=4096
CONFIG_PRE_CON_BUF_ADDR=0x04000000 CONFIG_PRE_CON_BUF_ADDR=0x04000000
# CONFIG_CONSOLE_MUX is not set # CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_FDT_FILE="armada-385-nbhw18-spl" CONFIG_DEFAULT_FDT_FILE="armada-385-hw18-spl"
# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x190 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x190
@ -50,7 +50,7 @@ CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_BOARD_FIXUP=y CONFIG_OF_BOARD_FIXUP=y
CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPL_OF_TRANSLATE=y
CONFIG_OF_LIST="armada-385-nbhw18-spl armada-385-nbhw18-v2" CONFIG_OF_LIST="armada-385-hw18-spl armada-385-hw18"
CONFIG_MULTI_DTB_FIT=y CONFIG_MULTI_DTB_FIT=y
CONFIG_FPGA_LATTICE_SSPI=y CONFIG_FPGA_LATTICE_SSPI=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y

0
include/configs/armada-385-nbhw17-v1.h → include/configs/armada-385-hw17.h
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0
include/configs/armada-385-nbhw18-v2.h → include/configs/armada-385-hw18.h
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