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Switch MPC86xADS and MPC885ADS boards to use cpuclk environment 

variable to set clock
Patch by Yuli Barcohen, 05 Jun 2005
This commit is contained in:
Wolfgang Denk 2006-03-12 01:55:43 +01:00
parent f47b661141
commit 8ff0208d31
5 changed files with 85 additions and 117 deletions
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4
CHANGELOG
View File

@ -2,6 +2,10 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
variable to set clock
Patch by Yuli Barcohen, 05 Jun 2005
* RPXlite configuration fixes * RPXlite configuration fixes
- Use correct flash sector size - Use correct flash sector size
- Use correct memory test end address - Use correct memory test end address

28
board/fads/fads.c
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@ -726,24 +726,23 @@ static void checkdboard(void)
int checkboard (void) int checkboard (void)
{ {
/* get revision from BCSR 3 */ #if defined(CONFIG_MPC86xADS)
puts ("Board: MPC86xADS\n");
#elif defined(CONFIG_MPC885ADS)
puts ("Board: MPC885ADS\n");
#else /* Only old ADS/FADS have got revision ID in BCSR3 */
uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
| (((*((uint *) BCSR3) >> 19) & 1) << 2) | (((*((uint *) BCSR3) >> 19) & 1) << 2)
| (((*((uint *) BCSR3) >> 16) & 3)); | (((*((uint *) BCSR3) >> 16) & 3));
puts ("Board: "); puts ("Board: ");
#if defined(CONFIG_FADS)
#if defined(CONFIG_MPC86xADS)
puts ("MPC86xADS");
#elif defined(CONFIG_MPC885ADS)
puts ("MPC885ADS");
r = 0; /* I've got NR (No Revision) board */
#elif defined(CONFIG_FADS)
puts ("FADS"); puts ("FADS");
checkdboard (); checkdboard ();
#else #else
puts ("ADS"); puts ("ADS");
#endif #endif
puts (" rev "); puts (" rev ");
switch (r) { switch (r) {
@ -758,13 +757,9 @@ int checkboard (void)
puts ("A - warning, read errata \n"); puts ("A - warning, read errata \n");
break; break;
case 0x03: case 0x03:
puts ("B \n"); puts ("B\n");
break; break;
#elif defined(CONFIG_MPC885ADS) #else /* FADS */
case 0x00:
puts ("NR\n");
break;
#else /* FADS and newer */
case 0x00: case 0x00:
puts ("ENG\n"); puts ("ENG\n");
break; break;
@ -776,6 +771,7 @@ int checkboard (void)
printf ("unknown (0x%x)\n", r); printf ("unknown (0x%x)\n", r);
return -1; return -1;
} }
#endif /* CONFIG_MPC86xADS */
return 0; return 0;
} }
@ -848,7 +844,7 @@ int pcmcia_init(void)
switch ((pcmp->pcmc_pipr >> 14) & 3) switch ((pcmp->pcmc_pipr >> 14) & 3)
#endif #endif
{ {
case 0x00 : case 0x03 :
printf("5V"); printf("5V");
v = 5; v = 5;
break; break;
@ -860,7 +856,7 @@ int pcmcia_init(void)
v = 5; v = 5;
#endif #endif
break; break;
case 0x03 : case 0x00 :
printf("5V, 3V and x.xV"); printf("5V, 3V and x.xV");
#ifdef CONFIG_FADS #ifdef CONFIG_FADS
v = 3; /* User lower voltage if supported! */ v = 3; /* User lower voltage if supported! */

125
board/fads/fads.h
View File

@ -55,18 +55,26 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif #endif
#undef CONFIG_BOOTARGS #define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTCOMMAND \
#define CONFIG_NFSBOOTCOMMAND \
"dhcp;" \ "dhcp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
"bootm" "bootm"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
"bootm fe080000"
#undef CONFIG_BOOTARGS
#undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
/* /*
* New MPC86xADS and Duet provide two Ethernet connectivity options: * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
* got FEC so FEC is the default. * got FEC so FEC is the default.
@ -89,7 +97,9 @@
#ifndef CONFIG_COMMANDS #ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DHCP \ | CFG_CMD_DHCP \
| CFG_CMD_ECHO \
| CFG_CMD_IMMAP \ | CFG_CMD_IMMAP \
| CFG_CMD_JFFS2 \ | CFG_CMD_JFFS2 \
| CFG_CMD_MII \ | CFG_CMD_MII \
@ -104,14 +114,16 @@
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=>" /* Monitor Command Prompt */ #define CFG_PROMPT "=>" /* Monitor Command Prompt */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* #undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@ -126,6 +138,7 @@
* (address mappings, register initial values, etc.) * (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here. * You should know what you are doing if you make changes here.
*/ */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Internal Memory Mapped Register * Internal Memory Mapped Register
*/ */
@ -148,6 +161,14 @@
#define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE 0x00000000
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
/*
* 2048 SDRAM rows
* 1000 factor s -> ms
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
#elif defined(CONFIG_FADS) /* Old/new FADS */ #elif defined(CONFIG_FADS) /* Old/new FADS */
#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
#else /* Old ADS */ #else /* Old ADS */
@ -223,9 +244,7 @@
* Cache Configuration * Cache Configuration
*/ */
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C configuration * I2C configuration
@ -277,31 +296,21 @@
* power management and some other internal clocks * power management and some other internal clocks
*/ */
#define SCCR_MASK SCCR_EBDF11 #define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) #define CFG_SCCR SCCR_TBS
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 * DER - Debug Enable Register
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
* set the PLL, the low-power modes and the reset control * Set to zero to prevent the processor from entering debug mode
*/
#ifndef CFG_PLPRCR
#define CFG_PLPRCR PLPRCR_TEXPS
#endif
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/ */
#define CFG_DER 0 #define CFG_DER 0
/* Because of the way the 860 starts up and assigns CS0 the /* Because of the way the 860 starts up and assigns CS0 the entire
* entire address space, we have to set the memory controller * address space, we have to set the memory controller differently.
* differently. Normally, you write the option register * Normally, you write the option register first, and then enable the
* first, and then enable the chip select by writing the * chip select by writing the base register. For CS0, you must write
* base register. For CS0, you must write the base register * the base register first, followed by the option register.
* first, followed by the option register. */
*/
/* /*
* Init Memory Controller: * Init Memory Controller:
@ -335,9 +344,6 @@
/* values according to the manual */ /* values according to the manual */
#define PCMCIA_MEM_ADDR ((uint)0xFF020000)
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
@ -396,59 +402,28 @@
#define BCSR4_TFPLDL ((uint)0x40000000) #define BCSR4_TFPLDL ((uint)0x40000000)
#define BCSR4_TPSQEL ((uint)0x20000000) #define BCSR4_TPSQEL ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
#define BCSR4_FETH_EN ((uint)0x08000000) #if defined(CONFIG_MPC823)
#define BCSR4_FETHCFG0 ((uint)0x04000000)
#define BCSR4_FETHFDE ((uint)0x02000000)
#define BCSR4_FETHCFG1 ((uint)0x00400000)
#define BCSR4_FETHRST ((uint)0x00200000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN ((uint)0x08000000) #define BCSR4_USB_EN ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED ((uint)0x04000000) #define BCSR4_USB_SPEED ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0 ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO ((uint)0x02000000) #define BCSR4_VCCO ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON ((uint)0x00800000) #define BCSR4_VIDEO_ON ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1 ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST ((uint)0x00200000) #define BCSR4_VIDEO_RST ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN ((uint)0x00100000) #define BCSR4_MODEM_EN ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE ((uint)0x00080000) #define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC823 */ #elif defined(CONFIG_MPC850)
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE ((uint)0x00080000) #define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC850 */ #elif defined(CONFIG_MPC860SAR)
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
#else /* MPC860T and other chips with FEC */
#define BCSR4_FETH_EN ((uint)0x08000000)
#define BCSR4_FETHCFG0 ((uint)0x04000000)
#define BCSR4_FETHFDE ((uint)0x02000000)
#define BCSR4_FETHCFG1 ((uint)0x00400000)
#define BCSR4_FETHRST ((uint)0x00200000)
#endif
/* BSCR5 exists on MPC86xADS and Duet ADS only */ /* BSCR5 exists on MPC86xADS and MPC885ADS only */
#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
@ -511,4 +486,4 @@
#define CFG_ATA_ALT_OFFSET 0x0000 #define CFG_ATA_ALT_OFFSET 0x0000
#define CONFIG_DISK_SPINUP_TIME 1000000 #define CONFIG_DISK_SPINUP_TIME 1000000
#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */

5
include/configs/MPC86xADS.h
View File

@ -21,7 +21,7 @@
#define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_MPC86xADS 1 /* new ADS */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
/* New MPC86xADS - pick one of these */ /* CPU type - pick one of these */
#define CONFIG_MPC866T 1 #define CONFIG_MPC866T 1
#undef CONFIG_MPC866P #undef CONFIG_MPC866P
#undef CONFIG_MPC859T #undef CONFIG_MPC859T
@ -34,6 +34,9 @@
#define CONFIG_BAUDRATE 38400 #define CONFIG_BAUDRATE 38400
#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ #define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 80000000
#define CONFIG_DRAM_50MHZ 1 #define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1

22
include/configs/MPC885ADS.h
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@ -1,17 +1,16 @@
/* /*
* A collection of structures, addresses, and values associated with * A collection of structures, addresses, and values associated with
* the Motorola DUET ADS board. Values common to all FADS family boards * the Motorola MPC885ADS board. Values common to all FADS family boards
* are in board/fads/fads.h * are in board/fads/fads.h
* *
* Copyright (C) 2003 Arabella Software Ltd. * Copyright (C) 2003-2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com> * Yuli Barcohen <yuli@arabellasw.com>
*/ */
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
/* Board type */ #define CONFIG_MPC885ADS 1 /* MPC885ADS board */
#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ #define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
@ -22,23 +21,14 @@
#define CONFIG_BAUDRATE 38400 #define CONFIG_BAUDRATE 38400
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) #define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
#define CONFIG_SDRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
)
#include "fads.h" #include "fads.h"
#undef CFG_SCCR
#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11)
#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)