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Merge branch '2019-05-28-master-imports' 

- Remove various dead code from DaVinci
- FAT fixes
This commit is contained in:
Tom Rini 2019-05-29 07:27:52 -04:00
parent 7c7919cd07 2a221fb64e
commit 93294caaeb
76 changed files with 171 additions and 6376 deletions
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4
Kconfig
View File

@ -389,7 +389,7 @@ config SPL_FIT_SIGNATURE
select SPL_RSA
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT"
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
@ -400,7 +400,7 @@ config SPL_LOAD_FIT
and passing the correct one to U-Boot.
config SPL_LOAD_FIT_FULL
bool "Enable SPL loading U-Boot as a FIT"
bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part

6
arch/arm/include/asm/mach-types.h
View File

@ -629,7 +629,6 @@
#define MACH_TYPE_ECIA 623
#define MACH_TYPE_CM4008 624
#define MACH_TYPE_P2001 625
#define MACH_TYPE_TWISTER 626
#define MACH_TYPE_MUDSHARK 627
#define MACH_TYPE_HB2 628
#define MACH_TYPE_IQ80332 629
@ -2716,7 +2715,6 @@
#define MACH_TYPE_VPNEXT_MPU 2747
#define MACH_TYPE_BCMRING_TABLET_V1 2748
#define MACH_TYPE_SGARM10 2749
#define MACH_TYPE_CM_T3517 2750
#define MACH_TYPE_OMAP3_CPS 2751
#define MACH_TYPE_AXAR1500_RECEIVER 2752
#define MACH_TYPE_WBD222 2753
@ -2960,7 +2958,6 @@
#define MACH_TYPE_AX8008 2999
#define MACH_TYPE_GNET_SGCE 3000
#define MACH_TYPE_PXWNAS_500_1000 3001
#define MACH_TYPE_EA20 3002
#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
#define MACH_TYPE_SEABOARD 3005
@ -3475,7 +3472,6 @@
#define MACH_TYPE_SGH_I710 3525
#define MACH_TYPE_INTEGREPROSCB 3526
#define MACH_TYPE_MONZA 3527
#define MACH_TYPE_CALIMAIN 3528
#define MACH_TYPE_MX6Q_SABREAUTO 3529
#define MACH_TYPE_GMA01X 3530
#define MACH_TYPE_SBC51 3531
@ -3600,7 +3596,6 @@
#define MACH_TYPE_TAISHAN 3653
#define MACH_TYPE_TOUCHLINK 3654
#define MACH_TYPE_STM32F103ZE 3655
#define MACH_TYPE_MCX 3656
#define MACH_TYPE_STM_NMHDK_FLI7610 3657
#define MACH_TYPE_TOP28X 3658
#define MACH_TYPE_OKL4VP_MICROVISOR 3659
@ -3775,7 +3770,6 @@
#define MACH_TYPE_IMXT_NAV 3829
#define MACH_TYPE_IMXT_FULL 3830
#define MACH_TYPE_AG09015 3831
#define MACH_TYPE_AM3517_MT_VENTOUX 3832
#define MACH_TYPE_DP1ARM9 3833
#define MACH_TYPE_PICASSO_M 3834
#define MACH_TYPE_VIDEO_GADGET 3835

19
arch/arm/mach-davinci/Kconfig
View File

@ -4,33 +4,17 @@ choice
prompt "DaVinci board select"
optional
config TARGET_IPAM390
bool "IPAM390 board"
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
select SUPPORT_SPL
config TARGET_DA850EVM
bool "DA850 EVM board"
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
select SUPPORT_SPL
config TARGET_EA20
bool "EA20 board"
select BOARD_LATE_INIT
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SOC_DA8XX
select SUPPORT_SPL
config TARGET_CALIMAIN
bool "Calimain board"
select SOC_DA850
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
select MACH_DAVINCI_DA850_EVM
@ -146,10 +130,7 @@ config SYS_DA850_PLL1_PLLDIV3
endif
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
source "board/omicron/calimain/Kconfig"
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT

31
arch/arm/mach-omap2/omap3/Kconfig
View File

@ -34,11 +34,6 @@ config TARGET_AM3517_EVM
select DM_SERIAL
imply CMD_DM
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
select OMAP3_GPIO_4
select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
@ -54,12 +49,6 @@ config TARGET_CM_T35
select OMAP3_GPIO_5
select OMAP3_GPIO_6 if LED_STATUS
config TARGET_CM_T3517
bool "CompuLab CM-T3517 boards"
select OMAP3_GPIO_2
select OMAP3_GPIO_5
select OMAP3_GPIO_6 if LED_STATUS
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
@ -112,20 +101,10 @@ config TARGET_OMAP3_PANDORA
select OMAP3_GPIO_4
select OMAP3_GPIO_6
config TARGET_ECO5PK
bool "ECO5PK"
select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_TRICORDER
bool "Tricorder"
select OMAP3_GPIO_2
config TARGET_MCX
bool "MCX"
select BOARD_LATE_INIT
select OMAP3_GPIO_2 if USB_EHCI_HCD
select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
select BOARD_LATE_INIT
@ -148,11 +127,6 @@ config TARGET_TAO3530
select OMAP3_GPIO_5
select OMAP3_GPIO_6
config TARGET_TWISTER
bool "Twister"
select OMAP3_GPIO_2
select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
@ -199,10 +173,8 @@ config SYS_SOC
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
@ -210,13 +182,10 @@ source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
source "board/lg/sniper/Kconfig"

12
board/8dtech/eco5pk/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_ECO5PK
config SYS_BOARD
default "eco5pk"
config SYS_VENDOR
default "8dtech"
config SYS_CONFIG_NAME
default "eco5pk"
endif

6
board/8dtech/eco5pk/MAINTAINERS
View File

@ -1,6 +0,0 @@
ECO5PK BOARD
M: Raphael Assenat <raph@8d.com>
S: Maintained
F: board/8dtech/eco5pk/
F: include/configs/eco5pk.h
F: configs/eco5pk_defconfig

8
board/8dtech/eco5pk/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Adapted from ti/evm/Makefile
obj-y := eco5pk.o

48
board/8dtech/eco5pk/eco5pk.c
View File

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
*
* Based on am3517evm.c
*
* Copyright (C) 2011-2012 8D Technologies inc.
* Copyright (C) 2009 Texas Instruments Incorporated
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/emac_defs.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <u-boot/crc.h>
#include <asm/mach-types.h>
#include "eco5pk.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
gpio_request(30, "RESOUT");
gpio_direction_output(30, 1);
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_ECO5_PK();
}

391
board/8dtech/eco5pk/eco5pk.h
View File

@ -1,391 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* eco5.h - Header file for the 8D Technologies ECO5 board.
*
* Based on am3517evm.h
* Based on ti/evm/evm.h
*
* Copyright (C) 2011 8D Technologies inc.
* Copyright (C) 2009 Texas Instruments Incorporated
*/
#ifndef _ECO5PK_H__
#define _ECO5PK_H__
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"ECO5 Board",
"NAND",
};
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_ECO5_PK() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
/* - ETH_nRESET*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
/* - CAM_RESET*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
\
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
/* - LCD_INI*/\
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
/* - LCD_ENVDD */\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
/* - LCD_QVGA/nVGA */\
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
/* - LCD_RESB */\
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
/* - LAN_INTR*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
/* LCD_EN_BACKLIGHT */\
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/* SYS_nRESWARM */\
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
/* - PEN_IRQ */\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
/* - VIO_1V8*/\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
#endif

12
board/Barix/ipam390/Kconfig
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@ -1,12 +0,0 @@
if TARGET_IPAM390
config SYS_BOARD
default "ipam390"
config SYS_VENDOR
default "Barix"
config SYS_CONFIG_NAME
default "ipam390"
endif

6
board/Barix/ipam390/MAINTAINERS
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@ -1,6 +0,0 @@
IPAM390 BOARD
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/Barix/ipam390/
F: include/configs/ipam390.h
F: configs/ipam390_defconfig

8
board/Barix/ipam390/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
obj-y += ipam390.o

229
board/Barix/ipam390/README.ipam390
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@ -1,229 +0,0 @@
Summary
=======
The README is for the boot procedure on the ipam390 board
In the context of U-Boot, the board is booted in three stages. The initial
bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
in the internal ROM. The RBL initializes the internal memory and then
depending on the exact board and pin configurations will initialize another
controller (such as NAND) to continue the boot process by loading
the secondary program loader (SPL). The SPL will initialize the system
further (some clocks, SDRAM). As on this board is used the falcon boot
mode, now 2 ways are possible depending on the GPIO 7_14 input pin,
connected with the "soft reset switch"
If this pin is logical 1 (high level):
spl code starts the kernel image without delay
If this pin is logical 0 (low level):
spl code starts the u-boot image
AIS is an image format defined by TI for the images that are to be loaded
to memory by the RBL. The image is divided into a series of sections and
the image's entry point is specified. Each section comes with meta data
like the target address the section is to be copied to and the size of the
section, which is used by the RBL to load the image. At the end of the
image the RBL jumps to the image entry point. The AIS format allows for
other things such as programming the clocks and SDRAM if the header is
programmed for it. We do not take advantage of this and instead use SPL as
it allows for additional flexibility (run-time detect of board revision,
loading the next image from a different media, etc).
Compilation
===========
run "tools/buildman/buildman -k ipam390" in the u-boot source tree.
Once this build completes you will have a ../current/ipam390/u-boot.ais file
that needs to be written to the nand flash.
Flashing the images to NAND
==========================
The AIS image can be written to NAND flash using the following commands.
Assuming that the network is configured and enabled and the u-boot.ais file
is tftp'able.
U-Boot > print upd_uboot
upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize}
U-Boot >
U-Boot > run upd_uboot
Using DaVinci-EMAC device
TFTP from server 192.168.1.1; our IP address is 192.168.20.71
Filename '/tftpboot/ipam390/u-boot.ais'.
Load address: 0xc0000000
Loading: ##################################
1.5 MiB/s
done
Bytes transferred = 493716 (78894 hex)
NAND erase.part: device 0 offset 0x20000, size 0x160000
Erasing at 0x160000 -- 100% complete.
OK
NAND write: device 0 offset 0x20000, size 0x78894
493716 bytes written: OK
U-Boot >
Recovery
========
In the case of a "bricked" board, you need to use the TI tools found
here[1] to create an uboot-uart-ais.bin file
- cd to the u-boot source tree
- compile the u-boot for the ipam390 board:
$ tools/buildman/buildman -k ipam390
-> Now we shall have u-boot.bin
- Create u-boot-uart-ais.bin
$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini ipam390-ais-uart.cfg \
-o ../current/ipam390/uboot-uart-ais.bin ./u-boot.bin@0xC1080000;
Note: The ipam390-ais-uart.cfg is found in the board directory
for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg
- We can now run bootloader on IPAM390 via UART using the command below:
$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin
NOTE: Do not cancel the command execution! The command takes 20+ seconds
to upload u-boot over serial and run it!
Outcome:
Waiting for the OMAP-L138...
(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse): Processing command 0: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 1: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 2: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 3: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 4: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 5: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 326516-Byte section to address 0xC1080000.
(AIS Parse): Processing command 6: 0x58535906.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Performing jump and close...
(AIS Parse): AIS complete. Jump to address 0xC1080000.
(AIS Parse): Waiting for DONE...
(AIS Parse): Boot completed successfully.
Operation completed successfully.
Falcon Bootmode (boot linux without booting U-Boot)
===================================================
The Falcon Mode extends this way allowing to start the Linux kernel directly
from SPL. A new command is added to U-Boot to prepare the parameters that SPL
must pass to the kernel, using ATAGS or Device Tree.
In normal mode, these parameters are generated each time before
loading the kernel, passing to Linux the address in memory where
the parameters can be read.
With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
informed to load it before running the kernel.
To boot the kernel, these steps under a Falcon-aware U-Boot are required:
1. Boot the board into U-Boot.
Use the "spl export" command to generate the kernel parameters area or the DT.
U-Boot runs as when it boots the kernel, but stops before passing the control
to the kernel.
Here the command sequence for the ipam390 board:
- load the linux kernel image into ram:
U-Boot > nand read c0100000 2 200000 400000
NAND read: device 0 offset 0x200000, size 0x400000
4194304 bytes read: OK
- generate the bootparms image:
U-Boot > spl export atags c0100000
## Booting kernel from Legacy Image at c0100000 ...
Image Name: Linux-3.5.1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2504280 Bytes = 2.4 MiB
Load Address: c0008000
Entry Point: c0008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
subcommand not supported
subcommand not supported
Argument image is now in RAM at: 0xc0000100
- copy the bootparms image into nand:
U-Boot > mtdparts
device nand0 <davinci_nand.0>, # parts = 6
#: name size offset mask_flags
0: u-boot-env 0x00020000 0x00000000 0
1: u-boot 0x00160000 0x00020000 0
2: bootparms 0x00020000 0x00180000 0
3: factory-info 0x00060000 0x001a0000 0
4: kernel 0x00400000 0x00200000 0
5: rootfs 0x07a00000 0x00600000 0
active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000
defaults:
mtdids : nand0=davinci_nand.0
mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)
U-Boot > nand erase.part bootparms
NAND erase.part: device 0 offset 0x180000, size 0x20000
Erasing at 0x180000 -- 100% complete.
OK
U-Boot > nand write c0000100 180000 20000
NAND write: device 0 offset 0x180000, size 0x20000
131072 bytes written: OK
U-Boot >
You can use also the predefined U-Boot Environment variable "setbootparms",
which will do all the above steps in one command:
U-Boot > print setbootparms
setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000
U-Boot > run setbootparms
NAND read: device 0 offset 0x200000, size 0x400000
4194304 bytes read: OK
## Booting kernel from Legacy Image at c0100000 ...
Image Name: Linux-3.5.1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2504280 Bytes = 2.4 MiB
Load Address: c0008000
Entry Point: c0008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
subcommand not supported
subcommand not supported
Argument image is now in RAM at: 0xc0000100
NAND erase.part: device 0 offset 0x180000, size 0x20000
Erasing at 0x180000 -- 100% complete.
OK
NAND write: device 0 offset 0x180000, size 0x20000
131072 bytes written: OK
U-Boot >
Links
=====
[1]
http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/

202
board/Barix/ipam390/ipam390-ais-uart.cfg
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@ -1,202 +0,0 @@
; General settings that can be overwritten in the host code
; that calls the AISGen library.
[General]
; Can be 8 or 16 - used in emifa
busWidth=8
; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
BootMode=UART
; 8,16,24 - used for SPI,I2C
;AddrWidth=8
; NO_CRC,SECTION_CRC,SINGLE_CRC
crcCheckType=NO_CRC
; This section allows setting the PLL0 system clock with a
; specified multiplier and divider as shown. The clock source
; can also be chosen for internal or external.
; |------24|------16|-------8|-------0|
; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
;[PLL0CONFIG]
;PLL0CFG0 = 0x00180001
;PLL0CFG1 = 0x00000205
[PLLANDCLOCKCONFIG]
PLL0CFG0 = 0x00180001
PLL0CFG1 = 0x00000205
PERIPHCLKCFG = 0x00000051
; This section allows setting up the PLL1. Usually this will
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: | RSVD | PLLDIV3|
[PLL1CONFIG]
PLL1CFG0 = 0x18010001
PLL1CFG1 = 0x00000002
; This section lets us configure the peripheral interface
; of the current booting peripheral (I2C, SPI, or UART).
; Use with caution. The format of the PERIPHCLKCFG field
; is as follows:
; SPI: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE|
;
; I2C: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE| CLKL | CLKH |
;
; UART: |------24|------16|-------8|-------0|
; | RSVD | OSR | DLH | DLL |
[PERIPHCLKCFG]
PERIPHCLKCFG = 0x00000051
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface.
; See PLL1CONFIG section for the format of the PLL1CFG fields.
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLL1CFG |
; PLL1CFG1: | PLL1CFG |
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
[EMIF3DDR]
PLL1CFG0 = 0x18010001
PLL1CFG1 = 0x00000002
DDRPHYC1R = 0x000000C2
SDCR = 0x0017C432
SDTIMR = 0x26922A09
SDTIMR2 = 0x4414C722
SDRCR = 0x00000498
CLK2XSRC = 0x00000000
; This section can be used to configure the EMIFA to use
; CS0 as an SDRAM interface. The fields required to do this
; are given below.
; |------24|------16|-------8|-------0|
; SDBCR: | SDBCR |
; SDTIMR: | SDTIMR |
; SDRSRPDEXIT: | SDRSRPDEXIT |
; SDRCR: | SDRCR |
; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
;[EMIF25SDRAM]
;SDBCR = 0x00004421
;SDTIMR = 0x42215810
;SDRSRPDEXIT = 0x00000009
;SDRCR = 0x00000410
;DIV4p5_CLK_ENABLE = 0x00000001
; This section can be used to configure the async chip selects
; of the EMIFA (CS2-CS5). The fields required to do this
; are given below.
; |------24|------16|-------8|-------0|
; A1CR: | A1CR |
; A2CR: | A2CR |
; A3CR: | A3CR |
; A4CR: | A4CR |
; NANDFCR: | NANDFCR |
;[EMIF25ASYNC]
;A1CR = 0x00000000
;A2CR = 0x00000000
;A3CR = 0x00000000
;A4CR = 0x00000000
;NANDFCR = 0x00000000
[EMIF25ASYNC]
A1CR = 0x00000000
A2CR = 0x04202110
A3CR = 0x00000000
A4CR = 0x00000000
NANDFCR = 0x00000012
; This section should be used in place of PLL0CONFIG when
; the I2C, SPI, or UART modes are being used. This ensures that
; the system PLL and the peripheral's clocks are changed together.
; See PLL0CONFIG section for the format of the PLL0CFG fields.
; See PERIPHCLKCFG section for the format of the CLKCFG field.
; |------24|------16|-------8|-------0|
; PLL0CFG0: | PLL0CFG |
; PLL0CFG1: | PLL0CFG |
; PERIPHCLKCFG: | CLKCFG |
;[PLLANDCLOCKCONFIG]
;PLL0CFG0 = 0x00180001
;PLL0CFG1 = 0x00000205
;PERIPHCLKCFG = 0x00010032
; This section should be used to setup the power state of modules
; of the two PSCs. This section can be included multiple times to
; allow the configuration of any or all of the device modules.
; |------24|------16|-------8|-------0|
; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
;[PSCCONFIG]
;LPSCCFG=
; This section allows setting of a single PINMUX register.
; This section can be included multiple times to allow setting
; as many PINMUX registers as needed.
; |------24|------16|-------8|-------0|
; REGNUM: | regNum |
; MASK: | mask |
; VALUE: | value |
;[PINMUX]
;REGNUM = 5
;MASK = 0x00FF0000
;VALUE = 0x00880000
; No Params required - simply include this section for the fast boot
; function to be called
;[FASTBOOT]
; This section allows setting up the PLL1. Usually this will
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: | RSVD | PLLDIV3|
;[PLL1CONFIG]
;PLL1CFG0 = 0x15010001
;PLL1CFG1 = 0x00000002
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface on ARM-boot D800K002 devices.
; |------24|------16|-------8|-------0|
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
;[ARM_EMIF3DDR_PATCHFXN]
;DDRPHYC1R = 0x000000C2
;SDCR = 0x0017C432
;SDTIMR = 0x26922A09
;SDTIMR2 = 0x4414C722
;SDRCR = 0x00000498
;CLK2XSRC = 0x00000000
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface on DSP-boot D800K002 devices.
; |------24|------16|-------8|-------0|
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
;[DSP_EMIF3DDR_PATCHFXN]
;DDRPHYC1R = 0x000000C4
;SDCR = 0x08134632
;SDTIMR = 0x26922A09
;SDTIMR2 = 0x0014C722
;SDRCR = 0x00000492
;CLK2XSRC = 0x00000000
;[INPUTFILE]
;FILENAME=u-boot.bin
;LOADADDRESS=0xC1080000
;ENTRYPOINTADDRESS=0xC1080000

335
board/Barix/ipam390/ipam390.c
View File

@ -1,335 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
* Based on:
* U-Boot:board/davinci/da8xxevm/da850evm.c
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <hwconfig.h>
#include <bootstage.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
#define HAS_RMII 1
#else
#define HAS_RMII 0
#endif
#endif /* CONFIG_DRIVER_TI_EMAC */
void dsp_lpsc_on(unsigned domain, unsigned int id)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
struct davinci_psc_regs *psc_regs;
psc_regs = davinci_psc0_regs;
mdstat = &psc_regs->psc0.mdstat[id];
mdctl = &psc_regs->psc0.mdctl[id];
ptstat = &psc_regs->ptstat;
ptcmd = &psc_regs->ptcmd;
while (*ptstat & (0x1 << domain))
;
if ((*mdstat & 0x1f) == 0x03)
return; /* Already on and enabled */
*mdctl |= 0x03;
*ptcmd = 0x1 << domain;
while (*ptstat & (0x1 << domain))
;
while ((*mdstat & 0x1f) != 0x03)
; /* Probably an overkill... */
}
static void dspwake(void)
{
unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
u32 val;
/* if the device is ARM only, return */
if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
return;
if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
return;
*resetvect++ = 0x1E000; /* DSP Idle */
/* clear out the next 10 words as NOP */
memset(resetvect, 0, sizeof(unsigned) * 10);
/* setup the DSP reset vector */
writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
val = readl(PSC0_MDCTL + (15 * 4));
val |= 0x100;
writel(val, (PSC0_MDCTL + (15 * 4)));
}
int misc_init_r(void)
{
dspwake();
return 0;
}
static const struct pinmux_config gpio_pins[] = {
/* GP7[14] selects bootmode*/
{ pinmux(16), 8, 3 }, /* GP7[14] */
};
const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
#else
PINMUX_ITEM(emac_pins_mii),
#endif
#endif
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
PINMUX_ITEM(uart0_pins_txrx),
PINMUX_ITEM(uart0_pins_rtscts),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_nand),
#endif
PINMUX_ITEM(gpio_pins),
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_UART0 }, /* console */
{ DAVINCI_LPSC_GPIO },
};
const int lpsc_size = ARRAY_SIZE(lpsc);
#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
#endif
#define REV_AM18X_EVM 0x100
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
* bit[0-3] Maximum cpu clock rate supported by onboard SoC
* 0000b - 300 MHz
* 0001b - 372 MHz
* 0010b - 408 MHz
* 0011b - 456 MHz
*/
u32 get_board_rev(void)
{
char *s;
u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
u32 rev = 0;
s = env_get("maxcpuclk");
if (s)
maxcpuclk = simple_strtoul(s, NULL, 10);
if (maxcpuclk >= 456000000)
rev = 3;
else if (maxcpuclk >= 408000000)
rev = 2;
else if (maxcpuclk >= 372000000)
rev = 1;
#ifdef CONFIG_DA850_AM18X_EVM
rev |= REV_AM18X_EVM;
#endif
return rev;
}
int board_early_init_f(void)
{
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
return 0;
}
int board_init(void)
{
irq_init();
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART0),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
&davinci_uart0_ctrl_regs->pwremu_mgmt);
#else
&davinci_uart2_ctrl_regs->pwremu_mgmt);
#endif
return 0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
static int init_led(int gpio, char *name, int val)
{
int ret;
ret = gpio_request(gpio, name);
if (ret)
return -1;
ret = gpio_direction_output(gpio, val);
if (ret)
return -1;
return gpio;
}
#define LED_ON 0
#define LED_OFF 1
#if !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress(int status)
{
static int red;
static int green;
if (red == 0)
red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
if (red != CONFIG_IPAM390_GPIO_LED_RED)
return;
if (green == 0)
green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green",
LED_OFF);
if (green != CONFIG_IPAM390_GPIO_LED_GREEN)
return;
switch (status) {
case BOOTSTAGE_ID_RUN_OS:
/*
* set normal state
* LED Red : on
* LED green: off
*/
gpio_set_value(red, LED_ON);
gpio_set_value(green, LED_OFF);
break;
case BOOTSTAGE_ID_MAIN_LOOP:
/*
* U-Boot operation
* LED Red : on
* LED green: on
*/
gpio_set_value(red, LED_ON);
gpio_set_value(green, LED_ON);
break;
}
}
#endif
#endif
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
int ret;
int bootmode = 0;
/*
* GP7[14] selects bootmode:
* 1: boot linux
* 0: boot u-boot
* if error accessing gpio boot U-Boot
*
* SPL bootmode
* 0: boot linux
* 1: boot u-boot
*/
ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode");
if (ret)
bootmode = 1;
if (!bootmode) {
ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE);
if (ret)
bootmode = 1;
}
if (!bootmode)
ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE);
if (!bootmode)
if (ret == 0)
bootmode = 1;
/*
* LED red : on
* LED green: off
*/
init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
return bootmode;
}
#endif

57
board/Barix/ipam390/u-boot-spl-ipam390.lds
View File

@ -1,57 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*/
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
} >.sram
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} >.sram
__image_copy_end = .;
.end :
{
*(.__end)
} >.sram
}

65
board/broadcom/bcmstb/bcmstb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Cisco Systems, Inc.
* (C) Copyright 2019 Synamedia
*
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
@ -9,7 +10,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/bootm.h>
#include <mach/sdhci.h>
#include <mach/timer.h>
#include <mmc.h>
#include <fdtdec.h>
@ -80,69 +80,6 @@ void enable_caches(void)
*/
}
static const phys_addr_t bcmstb_sdhci_address(u32 alias_index)
{
int node = 0;
int ret = 0;
char sdhci[16] = { 0 };
const void *fdt = gd->fdt_blob;
const char *path = NULL;
struct fdt_resource resource = { 0 };
if (!fdt) {
printf("%s: Invalid gd->fdt_blob\n", __func__);
return 0;
}
node = fdt_path_offset(fdt, "/aliases");
if (node < 0) {
printf("%s: Failed to find /aliases node\n", __func__);
return 0;
}
sprintf(sdhci, "sdhci%d", alias_index);
path = fdt_getprop(fdt, node, sdhci, NULL);
if (!path) {
printf("%s: Failed to find alias for %s\n", __func__, sdhci);
return 0;
}
node = fdt_path_offset(fdt, path);
if (node < 0) {
printf("%s: Failed to resolve BCMSTB SDHCI alias\n", __func__);
return 0;
}
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
"host", &resource);
if (ret) {
printf("%s: Failed to read BCMSTB SDHCI host resource\n",
__func__);
return 0;
}
return resource.start;
}
int board_mmc_init(bd_t *bis)
{
phys_addr_t sdhci_base_address = 0;
sdhci_base_address = bcmstb_sdhci_address(CONFIG_BCMSTB_SDHCI_INDEX);
if (!sdhci_base_address) {
sdhci_base_address = BCMSTB_SDHCI_BASE;
printf("%s: Assuming BCMSTB SDHCI address: 0x%p\n",
__func__, (void *)sdhci_base_address);
}
debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address);
bcmstb_sdhci_init(sdhci_base_address);
return 0;
}
int timer_init(void)
{
gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY);

12
board/compulab/cm_t3517/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_CM_T3517
config SYS_BOARD
default "cm_t3517"
config SYS_VENDOR
default "compulab"
config SYS_CONFIG_NAME
default "cm_t3517"
endif

6
board/compulab/cm_t3517/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM_T3517 BOARD
M: Igor Grinberg <grinberg@compulab.co.il>
S: Maintained
F: board/compulab/cm_t3517/
F: include/configs/cm_t3517.h
F: configs/cm_t3517_defconfig

7
board/compulab/cm_t3517/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
#
# Authors: Igor Grinberg <grinberg@compulab.co.il>
obj-y += cm_t3517.o mux.o

240
board/compulab/cm_t3517/cm_t3517.c
View File

@ -1,240 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Igor Grinberg <grinberg@compulab.co.il>
*/
#include <common.h>
#include <environment.h>
#include <status_led.h>
#include <net.h>
#include <netdev.h>
#include <usb.h>
#include <mmc.h>
#include <linux/compiler.h>
#include <linux/usb/musb.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/am35x_def.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/musb.h>
#include <asm/omap_musb.h>
#include <asm/ehci-omap.h>
#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"CM-T3517 board",
"NAND 128/512M",
};
#ifdef CONFIG_USB_MUSB_AM35X
static struct musb_hdrc_config cm_t3517_musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
static struct omap_musb_board_data cm_t3517_musb_board_data = {
.set_phy_power = am35x_musb_phy_power,
.clear_irq = am35x_musb_clear_irq,
.reset = am35x_musb_reset,
};
static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
#if defined(CONFIG_USB_MUSB_HOST)
.mode = MUSB_HOST,
#elif defined(CONFIG_USB_MUSB_GADGET)
.mode = MUSB_PERIPHERAL,
#else
#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
#endif
.config = &cm_t3517_musb_config,
.power = 250,
.platform_ops = &am35x_ops,
.board_data = &cm_t3517_musb_board_data,
};
static void cm_t3517_musb_init(void)
{
/*
* Set up USB clock/mode in the DEVCONF2 register.
* USB2.0 PHY reference clock is 13 MHz
*/
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
CONF2_VBDTCTEN | CONF2_DATPOL);
if (!musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
(void *)AM35XX_IPSS_USBOTGSS_BASE))
printf("Failed initializing AM35x MUSB!\n");
}
#else
static inline void am3517_evm_musb_init(void) {}
#endif
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
#endif
cm_t3517_musb_init();
return 0;
}
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
};
int misc_init_r(void)
{
cl_print_pcb_info();
omap_die_id_display();
return 0;
}
#if defined(CONFIG_MMC)
#define SB_T35_CD_GPIO 144
#define SB_T35_WP_GPIO 59
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
}
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONTROL_EFUSE_EMAC_LSB 0x48002380
#define CONTROL_EFUSE_EMAC_MSB 0x48002384
static int am3517_get_efuse_enetaddr(u8 *enetaddr)
{
u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
enetaddr[0] = (u8)((msb >> 16) & 0xff);
enetaddr[1] = (u8)((msb >> 8) & 0xff);
enetaddr[2] = (u8)(msb & 0xff);
enetaddr[3] = (u8)((lsb >> 16) & 0xff);
enetaddr[4] = (u8)((lsb >> 8) & 0xff);
enetaddr[5] = (u8)(lsb & 0xff);
return is_valid_ethaddr(enetaddr);
}
static inline int cm_t3517_init_emac(bd_t *bis)
{
int ret = cpu_eth_init(bis);
if (ret > 0)
return ret;
printf("Failed initializing EMAC! ");
return 0;
}
#else /* !CONFIG_DRIVER_TI_EMAC */
static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
#endif /* CONFIG_DRIVER_TI_EMAC */
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int cm_t3517_handle_mac_address(void)
{
unsigned char enetaddr[6];
int ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (ret) {
ret = am3517_get_efuse_enetaddr(enetaddr);
if (ret)
return ret;
}
if (!is_valid_ethaddr(enetaddr))
return -1;
return eth_env_set_enetaddr("ethaddr", enetaddr);
}
#define SB_T35_ETH_RST_GPIO 164
/*
* Routine: board_eth_init
* Description: initialize module and base-board Ethernet chips
*/
int board_eth_init(bd_t *bis)
{
int rc = 0, rc1 = 0;
rc1 = cm_t3517_handle_mac_address();
if (rc1)
printf("No MAC address found! ");
rc1 = cm_t3517_init_emac(bis);
if (rc1 > 0)
rc++;
rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
NULL, SB_T35_ETH_RST_GPIO);
if (rc1 > 0)
rc++;
return rc;
}
#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
#define CM_T3517_USB_HUB_RESET_GPIO 152
#define SB_T35_USB_HUB_RESET_GPIO 98
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(void)
{
cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */

235
board/compulab/cm_t3517/mux.c
View File

@ -1,235 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Igor Grinberg <grinberg@compulab.co.il>
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
void set_muxconf_regs(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
/* DataImage backlight */
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
/* SB-T35 SD/MMC WP GPIO59 */
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
/* SB-T35 Audio Enable GPIO61 */
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
/* SB-T35 Ethernet IRQ GPIO65 */
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
/* UART3 Console */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
/* RTC V3020 nCS GPIO163 */
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
/* SB-T35 Ethernet nRESET GPIO164 */
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
/* SB-T35 SD/MMC CD GPIO144 */
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
/* WIFI nRESET GPIO145 */
MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
/* USB1 PHY Reset GPIO 146 */
MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
/* USB2 PHY Reset GPIO 147 */
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
/* MMC1 */
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0));
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0));
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0));
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0));
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0));
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0));
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
/* I2C */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
/* SB-T35 USB HUB Reset GPIO98 */
MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
/* CM-T3517 USB HUB Reset GPIO152 */
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
/* RMII */
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
MUX_VAL(CP(RMII_MDIO_CLK), (M0));
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
/* Green LED GPIO186 */
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
/* SPI */
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
/* LCD reset GPIO157 */
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
/* RTC V3020 CS Enable GPIO160 */
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
/* SB-T35 LVDS Transmitter SHDN GPIO162 */
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
/* USB0 - mUSB */
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
/* USB1 EHCI */
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
/* USB2 EHCI */
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
/* SYS_BOOT */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
}

2
board/compulab/common/eeprom.c
View File

@ -410,7 +410,7 @@ struct eeprom_field layout_legacy[5] = {
#define layout_legacy layout_unknown
#endif
#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
#if defined(CONFIG_CM_T3X)
struct eeprom_field layout_v1[12] = {
{ "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
{ "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },

12
board/davinci/ea20/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_EA20
config SYS_BOARD
default "ea20"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "ea20"
endif

6
board/davinci/ea20/MAINTAINERS
View File

@ -1,6 +0,0 @@
EA20 BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/davinci/ea20/
F: include/configs/ea20.h
F: configs/ea20_defconfig

8
board/davinci/ea20/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
obj-y += ea20.o

337
board/davinci/ea20/ea20.c
View File

@ -1,337 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Based on da850evm.c, original Copyrights follow:
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/gpio.h>
#include "../../../drivers/video/da8xx-fb.h"
DECLARE_GLOBAL_DATA_PTR;
static const struct da8xx_panel lcd_panel = {
/* Casio COM57H531x */
.name = "Casio_COM57H531x",
.width = 640,
.height = 480,
.hfp = 12,
.hbp = 144,
.hsw = 30,
.vfp = 10,
.vbp = 35,
.vsw = 3,
.pxl_clk = 25000000,
.invert_pxl_clk = 0,
};
static const struct display_panel disp_panel = {
QVGA,
16,
16,
COLOR_ACTIVE,
};
static const struct lcd_ctrl_config lcd_cfg = {
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 255,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
};
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 2 },
{ pinmux(5), 1, 4 },
{ pinmux(5), 1, 5 }
};
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
{ pinmux(4), 2, 2 },
{ pinmux(4), 2, 3 }
};
/* UART0 pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux(3), 2, 7 },
{ pinmux(3), 2, 6 },
{ pinmux(3), 2, 4 },
{ pinmux(3), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
#define HAS_RMII 1
static const struct pinmux_config emac_pins[] = {
{ pinmux(14), 8, 2 },
{ pinmux(14), 8, 3 },
{ pinmux(14), 8, 4 },
{ pinmux(14), 8, 5 },
{ pinmux(14), 8, 6 },
{ pinmux(14), 8, 7 },
{ pinmux(15), 8, 1 },
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
#endif
#ifdef CONFIG_NAND_DAVINCI
const struct pinmux_config nand_pins[] = {
{ pinmux(7), 1, 0}, /* CS2 */
{ pinmux(7), 0, 1}, /* CS3 in three state*/
{ pinmux(7), 1, 4 }, /* EMA_WE */
{ pinmux(7), 1, 5 }, /* EMA_OE */
{ pinmux(9), 1, 0 }, /* EMA_D[7] */
{ pinmux(9), 1, 1 }, /* EMA_D[6] */
{ pinmux(9), 1, 2 }, /* EMA_D[5] */
{ pinmux(9), 1, 3 }, /* EMA_D[4] */
{ pinmux(9), 1, 4 }, /* EMA_D[3] */
{ pinmux(9), 1, 5 }, /* EMA_D[2] */
{ pinmux(9), 1, 6 }, /* EMA_D[1] */
{ pinmux(9), 1, 7 }, /* EMA_D[0] */
{ pinmux(12), 1, 5 }, /* EMA_A[2] */
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
{ pinmux(6), 1, 0 } /* EMA_CLK */
};
#endif
const struct pinmux_config gpio_pins[] = {
{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
{ pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
{ pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
{ pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
};
const struct pinmux_config lcd_pins[] = {
{ pinmux(17), 2, 1 }, /* LCD_D_0 */
{ pinmux(17), 2, 0 }, /* LCD_D_1 */
{ pinmux(16), 2, 7 }, /* LCD_D_2 */
{ pinmux(16), 2, 6 }, /* LCD_D_3 */
{ pinmux(16), 2, 5 }, /* LCD_D_4 */
{ pinmux(16), 2, 4 }, /* LCD_D_5 */
{ pinmux(16), 2, 3 }, /* LCD_D_6 */
{ pinmux(16), 2, 2 }, /* LCD_D_7 */
{ pinmux(18), 2, 1 }, /* LCD_D_8 */
{ pinmux(18), 2, 0 }, /* LCD_D_9 */
{ pinmux(17), 2, 7 }, /* LCD_D_10 */
{ pinmux(17), 2, 6 }, /* LCD_D_11 */
{ pinmux(17), 2, 5 }, /* LCD_D_12 */
{ pinmux(17), 2, 4 }, /* LCD_D_13 */
{ pinmux(17), 2, 3 }, /* LCD_D_14 */
{ pinmux(17), 2, 2 }, /* LCD_D_15 */
{ pinmux(18), 2, 6 }, /* LCD_PCLK */
{ pinmux(19), 2, 0 }, /* LCD_HSYNC */
{ pinmux(19), 2, 1 }, /* LCD_VSYNC */
{ pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
};
const struct pinmux_config halten_pin[] = {
{ pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
};
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
#endif
PINMUX_ITEM(uart_pins),
PINMUX_ITEM(i2c_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#endif
#ifdef CONFIG_VIDEO
PINMUX_ITEM(lcd_pins),
#endif
};
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART0 }, /* console */
{ DAVINCI_LPSC_GPIO },
{ DAVINCI_LPSC_LCDC }, /* LCD */
};
int board_early_init_f(void)
{
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* Set DISP_ON high to enable LCD output*/
gpio_direction_output(97, 1);
/* Set the RESETOUTn low */
gpio_direction_output(111, 0);
/* Set U0_SW0 low for UART0 as console*/
gpio_direction_output(106, 0);
/* Set U0_SW1 low for UART0 as console*/
gpio_direction_output(108, 0);
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
irq_init();
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
#ifdef CONFIG_NAND_DAVINCI
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab1cr); /* CS2 */
#endif
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART0),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart0_ctrl_regs->pwremu_mgmt);
/*
* Reconfigure the LCDC priority to the highest to ensure that
* the throughput/latency requirements for the LCDC are met.
*/
writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
&davinci_syscfg_regs->mstpri[2]);
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_EA20;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
unsigned char buf[2];
int ret;
/* PinMux for HALTEN */
if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
return 1;
/* Set HALTEN to high */
gpio_direction_output(134, 1);
/* Set fixed contrast settings for LCD via I2C potentiometer */
buf[0] = 0x00;
buf[1] = 0xd7;
ret = i2c_write(0x2e, 6, 1, buf, 2);
if (ret)
puts("\nContrast Settings FAILED\n");
/* Set LCD_B_PWR high to power up LCD Backlight*/
gpio_set_value(102, 1);
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
/*
* This board has a RMII PHY. However, the MDC line on the SOM
* must not be disabled (there is no MII PHY on the
* baseboard) via the GPIO2[6], because this pin
* disables at the same time the SPI flash.
*/
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */

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board/htkw/mcx/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MCX
config SYS_BOARD
default "mcx"
config SYS_VENDOR
default "htkw"
config SYS_CONFIG_NAME
default "mcx"
endif

6
board/htkw/mcx/MAINTAINERS
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@ -1,6 +0,0 @@
MCX BOARD
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
F: board/htkw/mcx/
F: include/configs/mcx.h
F: configs/mcx_defconfig

7
board/htkw/mcx/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
#
# Based on ti/evm/Makefile
obj-y := mcx.o

141
board/htkw/mcx/mcx.c
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@ -1,141 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
*
* Based on ti/evm/evm.c
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/arch/dss.h>
#include <asm/arch/clock.h>
#include <errno.h>
#include <i2c.h>
#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
#include "mcx.h"
DECLARE_GLOBAL_DATA_PTR;
#define HOT_WATER_BUTTON 42
#define LCD_OUTPUT 55
/* Address of the framebuffer in RAM. */
#define FB_START_ADDRESS 0x88000000
#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
gpio_direction_output(LCD_OUTPUT, 0);
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
puts("Failed to get hot-water-button pin\n");
return -ENODEV;
}
gpio_direction_input(HOT_WATER_BUTTON);
/*
* if hot-water-button is pressed
* change bootcmd
*/
if (gpio_get_value(HOT_WATER_BUTTON))
return 0;
env_set("bootcmd", "run swupdate");
return 0;
}
#endif
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_MCX();
}
#if defined(CONFIG_MMC_OMAP_HS)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct panel_config lcd_cfg = {
.timing_h = PANEL_TIMING_H(40, 40, 48),
.timing_v = PANEL_TIMING_V(29, 13, 3),
.pol_freq = 0x00003000, /* Pol Freq */
.divisor = 0x0001000E,
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
.lcd_size = PANEL_LCD_SIZE(800, 480),
.gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
int board_video_init(void)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
void *fb;
fb = (void *)FB_START_ADDRESS;
lcd_cfg.frame_buffer = fb;
setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
omap3_dss_panel_config(&lcd_cfg);
omap3_dss_enable();
return 0;
}
#endif

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board/htkw/mcx/mcx.h
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@ -1,400 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
*
* Based on ti/evm/evm.h
*/
#ifndef _AM3517EVM_H_
#define _AM3517EVM_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"HTKW mcx Board",
"NAND",
};
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_MCX() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
/* GPIO_43 LCD buffer enable */ \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
/* GPIO_57 TS_PenIRQn */\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
/* GPIO_58 ETHERNET RESET */\
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
/* GPIO_61 SD-CARD CD */ \
MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
/* GPIO_62 Nand write protect, keep enabled */ \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* GPIO_65 SD-CARD WP */\
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
/* GPIO_131 LCD Enable */ \
MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
/* GPIO_132 USB host Enable */\
MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
/* GPIO_133 HDMI PD */\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
\
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
/* GPIO_152 USB phy2 reset */\
MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
/* GPIO_153 */\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
/* GPIO_154 USB phy1 reset */\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
/* GPIO_155 TS_BUSY */\
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
/* GPIO_170 Touchscreen ISR */\
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat7 */\
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat4 */\
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat5 */\
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat6 */\
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat3 */\
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
/* CCDC_FIELD: gpio_95, uP-TXD4 */ \
MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
/* CCDC_HD: gpio_96, uP-RTS4# */ \
MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
/* CCDC_VD: gpio_97, uP-CTS4# */ \
MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
/* CCDC_WEN: gpio_98, uP-RXD4 */ \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
/* JTAG */\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
#endif

12
board/omicron/calimain/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_CALIMAIN
config SYS_BOARD
default "calimain"
config SYS_VENDOR
default "omicron"
config SYS_CONFIG_NAME
default "calimain"
endif

7
board/omicron/calimain/MAINTAINERS
View File

@ -1,7 +0,0 @@
CALIMAIN BOARD
M: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
M: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
S: Maintained
F: board/omicron/calimain/
F: include/configs/calimain.h
F: configs/calimain_defconfig

8
board/omicron/calimain/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
obj-y := calimain.o

145
board/omicron/calimain/calimain.c
View File

@ -1,145 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 OMICRON electronics GmbH
*
* Based on da850evm.c. Original Copyrights follow:
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/timer_defs.h>
#include "../../../drivers/gpio/da8xx_gpio.h"
DECLARE_GLOBAL_DATA_PTR;
#define CALIMAIN_HWVERSION_MASK 0x7f000000
#define CALIMAIN_HWVERSION_SHIFT 24
/* Hardware version pinmux settings */
const struct pinmux_config hwversion_pins[] = {
{ pinmux(16), 8, 2 }, /* GP7[15] */
{ pinmux(16), 8, 3 }, /* GP7[14] */
{ pinmux(16), 8, 4 }, /* GP7[13] */
{ pinmux(16), 8, 5 }, /* GP7[12] */
{ pinmux(16), 8, 6 }, /* GP7[11] */
{ pinmux(16), 8, 7 }, /* GP7[10] */
{ pinmux(17), 8, 0 }, /* GP7[9] */
{ pinmux(17), 8, 1 } /* GP7[8] */
};
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(emac_pins_mii),
PINMUX_ITEM(emac_pins_mdio),
PINMUX_ITEM(emifa_pins_nor),
PINMUX_ITEM(emifa_pins_cs2),
PINMUX_ITEM(emifa_pins_cs3),
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
};
const int lpsc_size = ARRAY_SIZE(lpsc);
/* read board revision from GPIO7[8..14] */
u32 get_board_rev(void)
{
lpsc_on(DAVINCI_LPSC_GPIO);
if (davinci_configure_pin_mux(hwversion_pins,
ARRAY_SIZE(hwversion_pins)) != 0)
return 0xffffffff;
return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK)
>> CALIMAIN_HWVERSION_SHIFT;
}
/*
* determine the oscillator frequency depending on the board revision
*
* rev 0x00 ... 25 MHz oscillator
* rev 0x01 ... 24 MHz oscillator
*/
int calimain_get_osc_freq(void)
{
u32 rev;
int freq;
rev = get_board_rev();
switch (rev) {
case 0x00:
freq = 25000000;
break;
default:
freq = 24000000;
break;
}
return freq;
}
int board_init(void)
{
int val;
irq_init();
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
#ifdef CONFIG_DRIVER_TI_EMAC
/* select emac MII mode */
val = readl(&davinci_syscfg_regs->cfgchip3);
val &= ~(1 << 8);
writel(val, &davinci_syscfg_regs->cfgchip3);
#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_HW_WATCHDOG
davinci_hw_watchdog_enable();
#endif
printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq());
printf("Board revision: %d\n", get_board_rev());
return 0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
davinci_hw_watchdog_reset();
}
#endif

12
board/technexion/twister/Kconfig
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@ -1,12 +0,0 @@
if TARGET_TWISTER
config SYS_BOARD
default "twister"
config SYS_VENDOR
default "technexion"
config SYS_CONFIG_NAME
default "twister"
endif

6
board/technexion/twister/MAINTAINERS
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@ -1,6 +0,0 @@
TWISTER BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/technexion/twister/
F: include/configs/twister.h
F: configs/twister_defconfig

7
board/technexion/twister/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
#
# Based on ti/evm/Makefile
obj-y := twister.o

160
board/technexion/twister/twister.c
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@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
#include <spl.h>
#include <mmc.h>
#include <asm/gpio.h>
#include <usb.h>
#include <asm/ehci-omap.h>
#include "twister.h"
DECLARE_GLOBAL_DATA_PTR;
/* Timing definitions for Ethernet Controller */
static const u32 gpmc_smc911[] = {
NET_GPMC_CONFIG1,
NET_GPMC_CONFIG2,
NET_GPMC_CONFIG3,
NET_GPMC_CONFIG4,
NET_GPMC_CONFIG5,
NET_GPMC_CONFIG6,
};
static const u32 gpmc_XR16L2751[] = {
XR16L2751_GPMC_CONFIG1,
XR16L2751_GPMC_CONFIG2,
XR16L2751_GPMC_CONFIG3,
XR16L2751_GPMC_CONFIG4,
XR16L2751_GPMC_CONFIG5,
XR16L2751_GPMC_CONFIG6,
};
#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
/* Chip select 1 and 3 are used for XR16L2751 UART controller */
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
XR16L2751_UART1_BASE, GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
XR16L2751_UART2_BASE, GPMC_SIZE_16M);
gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
return 0;
}
#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
char *eth_addr;
struct tam3517_module_info info;
int ret;
omap_die_id_display();
eth_addr = env_get("ethaddr");
if (eth_addr)
return 0;
TAM3517_READ_EEPROM(&info, ret);
if (!ret)
TAM3517_READ_MAC_FROM_EEPROM(&info);
return 0;
}
#endif
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_TWISTER();
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_initialize();
#endif
/* init cs for extern lan */
enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
#ifdef CONFIG_SMC911X
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
#else
return 0;
#endif
}
#if defined(CONFIG_MMC_OMAP_HS)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
/*
* Do board specific preparation before SPL
* Linux boot
*/
void spl_board_prepare_for_linux(void)
{
/* init cs for extern lan */
enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
}
int spl_start_uboot(void)
{
int val = 0;
if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
gpio_direction_input(SPL_OS_BOOT_KEY);
val = gpio_get_value(SPL_OS_BOOT_KEY);
gpio_free(SPL_OS_BOOT_KEY);
}
return val;
}
#endif

400
board/technexion/twister/twister.h
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@ -1,400 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2010 TechNexion Ltd.
*/
#ifndef _TAM3517_H_
#define _TAM3517_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"TAM3517 TWISTER Board",
"NAND",
};
#define XR16L2751_GPMC_CONFIG1 0x00000000
#define XR16L2751_GPMC_CONFIG2 0x001e1e01
#define XR16L2751_GPMC_CONFIG3 0x00080300
#define XR16L2751_GPMC_CONFIG4 0x1c091c09
#define XR16L2751_GPMC_CONFIG5 0x04181f1f
#define XR16L2751_GPMC_CONFIG6 0x00000FCF
#define XR16L2751_UART1_BASE 0x21000000
#define XR16L2751_UART2_BASE 0x23000000
/* GPIO used to select between U-Boot and kernel */
#define SPL_OS_BOOT_KEY 55
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_TWISTER() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
/* CardDetect */\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
/* - VIO_1V8*/\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
/* hsusb1_dir */\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
/* hsusb1_nxt */\
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
#endif

12
board/teejet/mt_ventoux/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MT_VENTOUX
config SYS_BOARD
default "mt_ventoux"
config SYS_VENDOR
default "teejet"
config SYS_CONFIG_NAME
default "mt_ventoux"
endif

6
board/teejet/mt_ventoux/MAINTAINERS
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@ -1,6 +0,0 @@
MT_VENTOUX BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/teejet/mt_ventoux/
F: include/configs/mt_ventoux.h
F: configs/mt_ventoux_defconfig

7
board/teejet/mt_ventoux/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
#
# Based on ti/evm/Makefile
obj-y := mt_ventoux.o

342
board/teejet/mt_ventoux/mt_ventoux.c
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@ -1,342 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*/
#include <common.h>
#include <netdev.h>
#include <malloc.h>
#include <fpga.h>
#include <video_fb.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/dss.h>
#include <asm/arch/clock.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
#include "mt_ventoux.h"
DECLARE_GLOBAL_DATA_PTR;
#define BUZZER 140
#define SPEAKER 141
#define USB1_PWR 127
#define USB2_PWR 149
#ifndef CONFIG_FPGA
#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
#endif
#define FPGA_RESET 62
#define FPGA_PROG 116
#define FPGA_CCLK 117
#define FPGA_DIN 118
#define FPGA_INIT 119
#define FPGA_DONE 154
#define LCD_PWR 138
#define LCD_PON_PIN 139
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct {
u32 xres;
u32 yres;
} panel_resolution[] = {
{ 480, 272 },
{ 800, 480 }
};
static struct panel_config lcd_cfg[] = {
{
.timing_h = PANEL_TIMING_H(40, 5, 2),
.timing_v = PANEL_TIMING_V(8, 8, 2),
.pol_freq = 0x00003000, /* Pol Freq */
.divisor = 0x00010033, /* 9 Mhz Pixel Clock */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
.gfx_format = GFXFORMAT_RGB24_UNPACKED,
},
{
.timing_h = PANEL_TIMING_H(20, 192, 4),
.timing_v = PANEL_TIMING_V(2, 20, 10),
.pol_freq = 0x00004000, /* Pol Freq */
.divisor = 0x0001000E, /* 36Mhz Pixel Clock */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
.gfx_format = GFXFORMAT_RGB24_UNPACKED,
}
};
#endif
/* Timing definitions for FPGA */
static const u32 gpmc_fpga[] = {
FPGA_GPMC_CONFIG1,
FPGA_GPMC_CONFIG2,
FPGA_GPMC_CONFIG3,
FPGA_GPMC_CONFIG4,
FPGA_GPMC_CONFIG5,
FPGA_GPMC_CONFIG6,
};
#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif
static inline void fpga_reset(int nassert)
{
gpio_set_value(FPGA_RESET, !nassert);
}
int fpga_pgm_fn(int nassert, int nflush, int cookie)
{
debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
gpio_set_value(FPGA_PROG, !nassert);
return nassert;
}
int fpga_init_fn(int cookie)
{
return !gpio_get_value(FPGA_INIT);
}
int fpga_done_fn(int cookie)
{
return gpio_get_value(FPGA_DONE);
}
int fpga_pre_config_fn(int cookie)
{
debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
/* Setting GPIOs for programming Mode */
gpio_request(FPGA_RESET, "FPGA_RESET");
gpio_direction_output(FPGA_RESET, 1);
gpio_request(FPGA_PROG, "FPGA_PROG");
gpio_direction_output(FPGA_PROG, 1);
gpio_request(FPGA_CCLK, "FPGA_CCLK");
gpio_direction_output(FPGA_CCLK, 1);
gpio_request(FPGA_DIN, "FPGA_DIN");
gpio_direction_output(FPGA_DIN, 0);
gpio_request(FPGA_INIT, "FPGA_INIT");
gpio_direction_input(FPGA_INIT);
gpio_request(FPGA_DONE, "FPGA_DONE");
gpio_direction_input(FPGA_DONE);
/* Be sure that signal are deasserted */
gpio_set_value(FPGA_RESET, 1);
gpio_set_value(FPGA_PROG, 1);
return 0;
}
int fpga_post_config_fn(int cookie)
{
debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
fpga_reset(true);
udelay(100);
fpga_reset(false);
return 0;
}
/* Write program to the FPGA */
int fpga_wr_fn(int nassert_write, int flush, int cookie)
{
gpio_set_value(FPGA_DIN, nassert_write);
return nassert_write;
}
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
gpio_set_value(FPGA_CCLK, assert_clk);
return assert_clk;
}
xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_init_fn,
fpga_done_fn,
fpga_wr_fn,
fpga_post_config_fn,
};
xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)&mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
static void mt_ventoux_init_fpga(void)
{
fpga_pre_config_fn(0);
/* Setting CS1 for FPGA access */
enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
FPGA_BASE_ADDR, GPMC_SIZE_128M);
fpga_init();
fpga_add(fpga_xilinx, &fpga);
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
mt_ventoux_init_fpga();
/* GPIO_140: speaker #mute */
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
/* GPIO_141: Buzz Hi */
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
/* Turning off the buzzer */
gpio_request(BUZZER, "BUZZER_MUTE");
gpio_request(SPEAKER, "SPEAKER");
gpio_direction_output(BUZZER, 0);
gpio_direction_output(SPEAKER, 0);
/* Activate USB power */
gpio_request(USB1_PWR, "USB1_PWR");
gpio_request(USB2_PWR, "USB2_PWR");
gpio_direction_output(USB1_PWR, 1);
gpio_direction_output(USB2_PWR, 1);
return 0;
}
#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
char *eth_addr;
struct tam3517_module_info info;
int ret;
TAM3517_READ_EEPROM(&info, ret);
omap_die_id_display();
if (ret)
return 0;
eth_addr = env_get("ethaddr");
if (!eth_addr)
TAM3517_READ_MAC_FROM_EEPROM(&info);
TAM3517_PRINT_SOM_INFO(&info);
return 0;
}
#endif
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_MT_VENTOUX();
}
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int board_eth_init(bd_t *bis)
{
davinci_emac_initialize();
return 0;
}
#if defined(CONFIG_MMC_OMAP_HS) && \
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
int board_video_init(void)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
struct panel_config *panel = &lcd_cfg[0];
char *s;
u32 index = 0;
void *fb;
fb = (void *)0x88000000;
s = env_get("panel");
if (s) {
index = simple_strtoul(s, NULL, 10);
if (index < ARRAY_SIZE(lcd_cfg))
panel = &lcd_cfg[index];
else
return 0;
}
panel->frame_buffer = fb;
printf("Panel: %dx%d\n", panel_resolution[index].xres,
panel_resolution[index].yres);
panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
(panel_resolution[index].xres - 1);
gpio_request(LCD_PWR, "LCD Power");
gpio_request(LCD_PON_PIN, "LCD Pon");
gpio_direction_output(LCD_PWR, 0);
gpio_direction_output(LCD_PON_PIN, 1);
setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
omap3_dss_panel_config(panel);
omap3_dss_enable();
return 0;
}
#endif

403
board/teejet/mt_ventoux/mt_ventoux.h
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@ -1,403 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
*
* Author: Hardy Weng <hardy.weng@technexion.com>
*
* Copyright (C) 2010 TechNexion Ltd.
*/
#ifndef _MT_VENTOUX_H_
#define _MT_VENTOUX_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"Teejet MT_VENTOUX Board",
"NAND",
};
/* FPGA CS1 configuration */
#define FPGA_GPMC_CONFIG1 0x00001200
#define FPGA_GPMC_CONFIG2 0x00161f00
#define FPGA_GPMC_CONFIG3 0x00040400
#define FPGA_GPMC_CONFIG4 0x120c1f08
#define FPGA_GPMC_CONFIG5 0x001e161f
#define FPGA_GPMC_CONFIG6 0x96080fcf
#define FPGA_BASE_ADDR 0x20000000
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_MT_VENTOUX() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
/* GPIO 55 : NFS */\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
/*GPIO_62: FPGA_RESET */ \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
/* GPIO_64*/ \
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
/* GPIO_126: CardDetect */\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
/*GPIO_128 */ \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
/* GPIO_138: LCD_ENVD */\
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
/* GPIO_139: LCD_PON */\
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \
/* GPIO_116: FPGA_PROG */ \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
/* GPIO_117: FPGA_CCLK */ \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
/* GPIO_118: FPGA_DIN */ \
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
/* GPIO_119: FPGA_INIT */ \
\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
/*GPIO_152: Ignition Sense */ \
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
/*GPIO_153: Power Button Sense */ \
MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
/* GPIO_154: FPGA_DONE */ \
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \
/* GPIO_155: CA8_irq */ \
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
/* GPIO_149: USB status 2 */\
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
/* GPIO_150: USB status 1 */\
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
/* gpt9_pwm */\
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
/* gpt10_pwm */\
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
/* gpt8_pwm */\
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
/* gpt11_pwm */\
\
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
/*GPIO_163 : TS_PENIRQ*/ \
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \
/*GPIO_164 : MMC */\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
/* GPIO94 */\
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
/* GPIO95: #Enable Output */\
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
/* GPIO 99: #SOM_PWR_OFF */\
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
/* GPIO_100: #power out */\
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
/* GPIO_102 */\
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
/* GPIO_170: auto update */\
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
/* gpio_10 */\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
/* gpio_24 */\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
/* gpio_26 */\
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
/* gpio_29 */\
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
#endif

8
cmd/Kconfig
View File

@ -1425,14 +1425,6 @@ config CMD_CLS
Enable the 'cls' command which clears the screen contents
on video frame buffer.
config CMD_DISPLAY
bool "Enable the 'display' command, for character displays"
help
(this needs porting to driver model)
This enables the 'display' command which allows a string to be
displayed on a simple board-specific display. Implement
display_putc() to use it.
config CMD_EFIDEBUG
bool "efidebug - display/configure UEFI environment"
depends on EFI_LOADER

1
cmd/Makefile
View File

@ -45,7 +45,6 @@ obj-$(CONFIG_CMD_SOUND) += sound.o
ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
obj-$(CONFIG_CMD_DISPLAY) += display.o
obj-$(CONFIG_CMD_DTIMG) += dtimg.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o

53
cmd/display.c
View File

@ -1,53 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <command.h>
#include <led-display.h>
#undef DEBUG_DISP
int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
/* Clear display */
display_set(DISPLAY_CLEAR | DISPLAY_HOME);
if (argc < 2)
return (0);
for (i = 1; i < argc; i++) {
char *p = argv[i];
if (i > 1) { /* Insert a space between strings */
display_putc(' ');
}
while ((*p)) {
#ifdef DEBUG_DISP
putc(*p);
#endif
display_putc(*p++);
}
}
#ifdef DEBUG_DISP
putc('\n');
#endif
return (0);
}
/***************************************************/
U_BOOT_CMD(
display, CONFIG_SYS_MAXARGS, 1, do_display,
"display string on dot matrix display",
"[<string>]\n"
" - with <string> argument: display <string> on dot matrix display\n"
" - without arguments: clear dot matrix display"
);

1
configs/bcm7260_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_EFI_PARTITION=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
# CONFIG_EFI_LOADER is not set

1
configs/bcm7445_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_DM_SPI_FLASH=y

37
configs/calimain_defconfig
View File

@ -1,37 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_TARGET_CALIMAIN=y
CONFIG_DA850_LOWLEVEL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Calimain > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_DA8XX_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y

60
configs/cm_t3517_defconfig
View File

@ -1,60 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_CM_T3517=y
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3517 # "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=186
CONFIG_LED_STATUS_STATE=2
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_MII=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2D000000
CONFIG_SMC911X_32_BIT=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_VIDEO_OMAP3=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y

48
configs/ea20_defconfig
View File

@ -1,48 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_TARGET_EA20=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ea20 > "
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DA8XX_GPIO=y
CONFIG_SYS_I2C_DAVINCI=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set

45
configs/eco5pk_defconfig
View File

@ -1,45 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_ECO5PK=y
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_BOOTDELAY=10
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

45
configs/ipam390_defconfig
View File

@ -1,45 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0xc1080000
CONFIG_TARGET_IPAM390=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00180000
CONFIG_CMD_SPL_WRITE_SIZE=0x400
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)"
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DA8XX_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y

58
configs/mcx_defconfig
View File

@ -1,58 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_MCX=y
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_VIDEO_OMAP3=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

54
configs/mt_ventoux_defconfig
View File

@ -1,54 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO_OMAP3=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

52
configs/twister_defconfig
View File

@ -1,52 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TWISTER=y
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_BOOTDELAY=10
CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="twister => "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00800000
CONFIG_CMD_SPL_WRITE_SIZE=0x400
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

26
doc/README.LED_display
View File

@ -1,26 +0,0 @@
LED display internal API
=======================================
This README describes the LED display API.
The API is defined by the include file include/led-display.h
The first step in to define CONFIG_CMD_DISPLAY in the board config file.
Then you need to provide the following functions to access LED display:
void display_set(int cmd);
This function should control the state of the LED display. Argument is
an ORed combination of the following values:
DISPLAY_CLEAR -- clear the display
DISPLAY_HOME -- set the position to the beginning of display
int display_putc(char c);
This function should display it's parameter on the LED display in the
current position. Returns the displayed character on success or -1 in
case of failure.
With this functions defined 'display' command will display it's
arguments on the LED display (or clear the display if called without
arguments).

81
drivers/mmc/bcmstb_sdhci.c
View File

@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Cisco Systems, Inc.
* (C) Copyright 2019 Synamedia
*
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
#include <common.h>
#include <dm.h>
#include <mach/sdhci.h>
#include <malloc.h>
#include <sdhci.h>
@ -36,32 +38,67 @@
*/
#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
/*
* This driver has only been tested with eMMC devices; SD devices may
* not work.
*/
int bcmstb_sdhci_init(phys_addr_t regbase)
struct sdhci_bcmstb_plat {
struct mmc_config cfg;
struct mmc mmc;
};
static int sdhci_bcmstb_bind(struct udevice *dev)
{
struct sdhci_host *host = NULL;
struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("%s: Failed to allocate memory\n", __func__);
return 1;
}
memset(host, 0, sizeof(*host));
host->name = BCMSTB_SDHCI_NAME;
host->ioaddr = (void *)regbase;
host->quirks = 0;
host->cfg.part_type = PART_TYPE_DOS;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
return add_sdhci(host,
BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static int sdhci_bcmstb_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
host->name = dev->name;
host->ioaddr = (void *)base;
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
ret = sdhci_setup_cfg(&plat->cfg, host,
BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
if (ret)
return ret;
upriv->mmc = &plat->mmc;
host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
}
static const struct udevice_id sdhci_bcmstb_match[] = {
{ .compatible = "brcm,bcm7425-sdhci" },
{ .compatible = "brcm,sdhci-brcmstb" },
{ }
};
U_BOOT_DRIVER(sdhci_bcmstb) = {
.name = "sdhci-bcmstb",
.id = UCLASS_MMC,
.of_match = sdhci_bcmstb_match,
.ops = &sdhci_ops,
.bind = sdhci_bcmstb_bind,
.probe = sdhci_bcmstb_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
.platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
};

9
fs/fat/fat.c
View File

@ -1134,11 +1134,12 @@ int fat_size(const char *filename, loff_t *size)
* expected to fail if passed a directory path:
*/
free(fsdata.fatbuf);
fat_itr_root(itr, &fsdata);
if (!fat_itr_resolve(itr, filename, TYPE_DIR)) {
ret = fat_itr_root(itr, &fsdata);
if (ret)
goto out_free_itr;
ret = fat_itr_resolve(itr, filename, TYPE_DIR);
if (!ret)
*size = 0;
ret = 0;
}
goto out_free_both;
}

165
fs/fat/fat_write.c
View File

@ -209,7 +209,8 @@ name11_12:
return 1;
}
static int flush_dir_table(fat_itr *itr);
static int new_dir_table(fat_itr *itr);
static int flush_dir(fat_itr *itr);
/*
* Fill dir_slot entries with appropriate name, id, and attr
@ -242,19 +243,18 @@ fill_dir_slot(fat_itr *itr, const char *l_name)
memcpy(itr->dent, slotptr, sizeof(dir_slot));
slotptr--;
counter--;
if (itr->remaining == 0)
flush_dir(itr);
/* allocate a cluster for more entries */
if (!fat_itr_next(itr))
if (!itr->dent && !itr->is_root && flush_dir_table(itr))
if (!itr->dent &&
(!itr->is_root || itr->fsdata->fatsize == 32) &&
new_dir_table(itr))
return -1;
}
if (!itr->dent && !itr->is_root)
/*
* don't care return value here because we have already
* finished completing an entry with name, only ending up
* no more entry left
*/
flush_dir_table(itr);
return 0;
}
@ -388,29 +388,23 @@ static __u32 determine_fatent(fsdata *mydata, __u32 entry)
}
/**
* set_cluster() - write data to cluster
* set_sectors() - write data to sectors
*
* Write 'size' bytes from 'buffer' into the specified cluster.
* Write 'size' bytes from 'buffer' into the specified sector.
*
* @mydata: data to be written
* @clustnum: cluster to be written to
* @startsect: sector to be written to
* @buffer: data to be written
* @size: bytes to be written (but not more than the size of a cluster)
* Return: 0 on success, -1 otherwise
*/
static int
set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
set_sectors(fsdata *mydata, u32 startsect, u8 *buffer, u32 size)
{
u32 idx = 0;
u32 startsect;
u32 nsects = 0;
int ret;
if (clustnum > 0)
startsect = clust_to_sect(mydata, clustnum);
else
startsect = mydata->rootdir_sect;
debug("clustnum: %d, startsect: %d\n", clustnum, startsect);
debug("startsect: %d\n", startsect);
if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
@ -429,17 +423,16 @@ set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
size -= mydata->sect_size;
}
} else if (size >= mydata->sect_size) {
idx = size / mydata->sect_size;
ret = disk_write(startsect, idx, buffer);
if (ret != idx) {
nsects = size / mydata->sect_size;
ret = disk_write(startsect, nsects, buffer);
if (ret != nsects) {
debug("Error writing data (got %d)\n", ret);
return -1;
}
startsect += idx;
idx *= mydata->sect_size;
buffer += idx;
size -= idx;
startsect += nsects;
buffer += nsects * mydata->sect_size;
size -= nsects * mydata->sect_size;
}
if (size) {
@ -457,6 +450,44 @@ set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
return 0;
}
/**
* set_cluster() - write data to cluster
*
* Write 'size' bytes from 'buffer' into the specified cluster.
*
* @mydata: data to be written
* @clustnum: cluster to be written to
* @buffer: data to be written
* @size: bytes to be written (but not more than the size of a cluster)
* Return: 0 on success, -1 otherwise
*/
static int
set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
{
return set_sectors(mydata, clust_to_sect(mydata, clustnum),
buffer, size);
}
static int
flush_dir(fat_itr *itr)
{
fsdata *mydata = itr->fsdata;
u32 startsect, sect_offset, nsects;
if (!itr->is_root || mydata->fatsize == 32)
return set_cluster(mydata, itr->clust, itr->block,
mydata->clust_size * mydata->sect_size);
sect_offset = itr->clust * mydata->clust_size;
startsect = mydata->rootdir_sect + sect_offset;
/* do not write past the end of rootdir */
nsects = min_t(u32, mydata->clust_size,
mydata->rootdir_size - sect_offset);
return set_sectors(mydata, startsect, itr->block,
nsects * mydata->sect_size);
}
static __u8 tmpbuf_cluster[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN);
/*
@ -590,18 +621,14 @@ static int find_empty_cluster(fsdata *mydata)
}
/*
* Write directory entries in itr's buffer to block device
* Allocate a cluster for additional directory entries
*/
static int flush_dir_table(fat_itr *itr)
static int new_dir_table(fat_itr *itr)
{
fsdata *mydata = itr->fsdata;
int dir_newclust = 0;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
if (set_cluster(mydata, itr->clust, itr->block, bytesperclust) != 0) {
printf("error: writing directory entry\n");
return -1;
}
dir_newclust = find_empty_cluster(mydata);
set_fatent_value(mydata, itr->clust, dir_newclust);
if (mydata->fatsize == 32)
@ -956,7 +983,10 @@ static dir_entry *find_directory_entry(fat_itr *itr, char *filename)
return itr->dent;
}
if (!itr->dent && !itr->is_root && flush_dir_table(itr))
/* allocate a cluster for more entries */
if (!itr->dent &&
(!itr->is_root || itr->fsdata->fatsize == 32) &&
new_dir_table(itr))
/* indicate that allocating dent failed */
itr->dent = NULL;
@ -1009,40 +1039,32 @@ again:
return 0;
}
/**
* normalize_longname() - check long file name and convert to lower case
*
* We assume here that the FAT file system is using an 8bit code page.
* Linux typically uses CP437, EDK2 assumes CP1250.
*
* @l_filename: preallocated buffer receiving the normalized name
* @filename: filename to normalize
* Return: 0 on success, -1 on failure
*/
static int normalize_longname(char *l_filename, const char *filename)
{
const char *p, legal[] = "!#$%&\'()-.@^`_{}~";
unsigned char c;
int name_len;
/* Check that the filename is valid */
for (p = filename; p < filename + strlen(filename); p++) {
c = *p;
if (('0' <= c) && (c <= '9'))
continue;
if (('A' <= c) && (c <= 'Z'))
continue;
if (('a' <= c) && (c <= 'z'))
continue;
if (strchr(legal, c))
continue;
/* extended code */
if ((0x80 <= c) && (c <= 0xff))
continue;
const char *p, illegal[] = "<>:\"/\\|?*";
if (strlen(filename) >= VFAT_MAXLEN_BYTES)
return -1;
for (p = filename; *p; ++p) {
if ((unsigned char)*p < 0x20)
return -1;
if (strchr(illegal, *p))
return -1;
}
/* Normalize it */
name_len = strlen(filename);
if (name_len >= VFAT_MAXLEN_BYTES)
/* should return an error? */
name_len = VFAT_MAXLEN_BYTES - 1;
memcpy(l_filename, filename, name_len);
l_filename[name_len] = 0; /* terminate the string */
downcase(l_filename, INT_MAX);
strcpy(l_filename, filename);
downcase(l_filename, VFAT_MAXLEN_BYTES);
return 0;
}
@ -1141,14 +1163,16 @@ int file_fat_write_at(const char *filename, loff_t pos, void *buffer,
memset(itr->dent, 0, sizeof(*itr->dent));
/* Set short name to set alias checksum field in dir_slot */
/* Calculate checksum for short name */
set_name(itr->dent, filename);
/* Set long name entries */
if (fill_dir_slot(itr, filename)) {
ret = -EIO;
goto exit;
}
/* Set attribute as archive for regular file */
/* Set short name entry */
fill_dentry(itr->fsdata, itr->dent, filename, 0, size, 0x20);
retdent = itr->dent;
@ -1171,8 +1195,7 @@ int file_fat_write_at(const char *filename, loff_t pos, void *buffer,
}
/* Write directory table to device */
ret = set_cluster(mydata, itr->clust, itr->block,
mydata->clust_size * mydata->sect_size);
ret = flush_dir(itr);
if (ret) {
printf("Error: writing directory entry\n");
ret = -EIO;
@ -1249,8 +1272,7 @@ static int delete_dentry(fat_itr *itr)
memset(dentptr, 0, sizeof(*dentptr));
dentptr->name[0] = 0xe5;
if (set_cluster(mydata, itr->clust, itr->block,
mydata->clust_size * mydata->sect_size) != 0) {
if (flush_dir(itr)) {
printf("error: writing directory entry\n");
return -EIO;
}
@ -1452,8 +1474,7 @@ int fat_mkdir(const char *new_dirname)
}
/* Write directory table to device */
ret = set_cluster(mydata, itr->clust, itr->block,
mydata->clust_size * mydata->sect_size);
ret = flush_dir(itr);
if (ret)
printf("Error: writing directory entry\n");

1
include/configs/bcm7260.h
View File

@ -19,7 +19,6 @@
#include "bcmstb.h"
#define BCMSTB_SDHCI_BASE 0xf0200300
#define BCMSTB_TIMER_LOW 0xf0412008
#define BCMSTB_TIMER_HIGH 0xf041200c
#define BCMSTB_TIMER_FREQUENCY 0xf0412020

1
include/configs/bcm7445.h
View File

@ -19,7 +19,6 @@
#include "bcmstb.h"
#define BCMSTB_SDHCI_BASE 0xf03e0200
#define BCMSTB_TIMER_LOW 0xf0412008
#define BCMSTB_TIMER_HIGH 0xf041200c
#define BCMSTB_TIMER_FREQUENCY 0xf0412020

11
include/configs/brppt1.h
View File

@ -66,7 +66,8 @@
#define NANDTGTS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"cfgscr=nand read ${cfgaddr} cfgscr && source ${cfgaddr}\0" \
"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
"root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
@ -104,7 +105,9 @@
#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMCSPI_TGTS \
"cfgscr=mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr}\0"
"cfgscr=mw ${dtbaddr} 0;" \
" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define MMCTGTS ""
#endif /* CONFIG_MMC */
@ -112,7 +115,9 @@ MMCSPI_TGTS \
#ifdef CONFIG_SPI
#define SPITGTS \
MMCSPI_TGTS \
"cfgscr=sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr}\0"
"cfgscr=mw ${dtbaddr} 0;" \
" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define SPITGTS ""
#endif /* CONFIG_SPI */

272
include/configs/calimain.h
View File

@ -1,272 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011-2014 OMICRON electronics GmbH
*
* Based on da850evm.h. Original Copyrights follow:
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Board
*/
#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
/*
* SoC Configuration
*/
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_HW_WATCHDOG
#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
#define CONFIG_SYS_WDT_PERIOD_LOW \
(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
/*
* PLL configuration
*/
#define CONFIG_SYS_DA850_PLL0_PLLM \
((calimain_get_osc_freq() == 25000000) ? 23 : 24)
#define CONFIG_SYS_DA850_PLL1_PLLM \
((calimain_get_osc_freq() == 25000000) ? 20 : 21)
/*
* DDR2 memory configuration
*/
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
(0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
(16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
(7 << DV_DDR_SDTMR1_RC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WTR_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Flash memory timing
*/
#define CONFIG_SYS_DA850_CS2CFG ( \
DAVINCI_ABCR_WSETUP(2) | \
DAVINCI_ABCR_WSTROBE(5) | \
DAVINCI_ABCR_WHOLD(3) | \
DAVINCI_ABCR_RSETUP(1) | \
DAVINCI_ABCR_RSTROBE(14) | \
DAVINCI_ABCR_RHOLD(0) | \
DAVINCI_ABCR_TA(3) | \
DAVINCI_ABCR_ASIZE_16BIT)
/* single 64 MB NOR flash device connected to CS2 and CS3 */
#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
DAVINCI_SYSCFG_SUSPSRC_EMAC | \
DAVINCI_SYSCFG_SUSPSRC_I2C)
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
#define CONFIG_SYS_MAX_FLASH_SECT \
((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
/*
* U-Boot general configuration
*/
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_LOADADDR 0xc0700000
#define CONFIG_MX_CYCLIC
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
#define CONFIG_RESET_TO_RETRY
/*
* Default environment settings
* gpio0 = button, gpio1 = led green, gpio2 = led red
* verify = n ... disable kernel checksum verification for faster booting
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"tftpdir=calimero\0" \
"flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
"erase 0x60800000 +0x400000; " \
"cp.b $loadaddr 0x60800000 $filesize\0" \
"flashrootfs=" \
"tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
"erase 0x60c00000 +0x2e00000; " \
"cp.b $loadaddr 0x60c00000 $filesize\0" \
"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
"protect off all; " \
"erase 0x60000000 +0x80000; " \
"cp.b $loadaddr 0x60000000 $filesize\0" \
"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
"erase 0x60080000 +0x780000; " \
"cp.b $loadaddr 0x60080000 $filesize\0" \
"erase_persistent=erase 0x63a00000 +0x600000;\0" \
"bootnor=setenv bootargs console=ttyS2,115200n8 " \
"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
"rootwait ethaddr=$ethaddr; " \
"gpio c 1; gpio s 2; bootm 0x60800000\0" \
"bootrlk=gpio s 1; gpio s 2;" \
"setenv bootargs console=ttyS2,115200n8 " \
"ethaddr=$ethaddr; bootm 0x60080000\0" \
"boottftp=setenv bootargs console=ttyS2,115200n8 " \
"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
"rootwait ethaddr=$ethaddr; " \
"tftpboot $loadaddr $tftpdir/uImage;" \
"gpio c 1; gpio s 2; bootm $loadaddr\0" \
"checkupdate=if test -n $update_flag; then " \
"echo Previous update failed - starting RLK; " \
"run bootrlk; fi; " \
"if test -n $initial_setup; then " \
"echo Running initial setup procedure; " \
"sleep 1; run flashall; fi\0" \
"product=accessory\0" \
"serial=XX12345\0" \
"checknor=" \
"if gpio i 0; then run bootnor; fi;\0" \
"checkrlk=" \
"if gpio i 0; then run bootrlk; fi;\0" \
"checkbutton=" \
"run checknor; sleep 1;" \
"run checknor; sleep 1;" \
"run checknor; sleep 1;" \
"run checknor; sleep 1;" \
"run checknor;" \
"gpio s 1; gpio s 2;" \
"echo ---- Release button to boot RLK ----;" \
"run checkrlk; sleep 1;" \
"run checkrlk; sleep 1;" \
"run checkrlk; sleep 1;" \
"run checkrlk; sleep 1;" \
"run checkrlk; sleep 1;" \
"run checkrlk;" \
"echo ---- Factory reset requested ----;" \
"gpio c 1;" \
"setenv factory_reset true;" \
"saveenv;" \
"run bootnor;\0" \
"flashall=run flashrlk;" \
"run flashkernel;" \
"run flashrootfs;" \
"setenv erase_datafs true;" \
"setenv initial_setup;" \
"saveenv;" \
"run bootnor;\0" \
"verify=n\0" \
"clearenv=protect off all;" \
"erase 0x60040000 +0x40000;\0" \
"altbootcmd=run bootrlk\0"
#define CONFIG_PREBOOT \
"echo Version: $ver; " \
"echo Serial: $serial; " \
"echo MAC: $ethaddr; " \
"echo Product: $product; " \
"gpio c 1; gpio c 2;"
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
/* initial stack pointer in internal SRAM */
#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
#ifndef __ASSEMBLY__
int calimain_get_osc_freq(void);
#endif
#include <asm/arch/hardware.h>
#endif /* __CONFIG_H */

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include/configs/cm_t3517.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013 CompuLab, Ltd.
* Author: Igor Grinberg <grinberg@compulab.co.il>
*
* Configuration settings for the CompuLab CM-T3517 board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_CM_T3517 /* working with CM-T3517 */
/*
* This is needed for the DMA stuff.
* Although the default iss 64, we still define it
* to be on the safe side once the default is changed.
*/
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
/*
* The early kernel mapping on ARM currently only maps from the base of DRAM
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
* so that leaves DRAM base to DRAM base + 0x4000 available.
*/
#define CONFIG_SYS_BOOTMAPSZ 0x4000
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/*
* select serial console configuration
*/
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/* USB */
#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#endif /* CONFIG_USB_MUSB_AM35X */
/* commands to include */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
#define CONFIG_I2C_MULTI_BUS
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"baudrate=115200\0" \
"console=ttyO2,115200n8\0" \
"netretry=yes\0" \
"mpurate=auto\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
"mmcrootfstype=ext4\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 2a0000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
/*
* Miscellaneous configurable options
*/
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
/*
* AM3517 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE (256 << 20)
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_NET_RETRY_COUNT 5
#endif /* CONFIG_CMD_NET */
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* Status LED */
#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
/* Display Configuration */
#define LCD_BPP LCD_COLOR16
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD
/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
#endif /* __CONFIG_H */

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include/configs/ea20.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Board
*/
#define CONFIG_USE_SPIFLASH
#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
#define CONFIG_PREBOOT
/*
* SoC Configuration
*/
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* I2C Configuration
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#endif
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#endif
/*
* U-Boot general configuration
*/
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_MX_CYCLIC
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
/* NAND Setup */
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_NO_SUBPAGE
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#endif
#if !defined(CONFIG_SYS_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_SIZE (16 << 10)
#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
/*
* Default environment and default scripts
* to update uboot and load kernel
*/
#define CONFIG_HOSTNAME "ea20"
#define CONFIG_EXTRA_ENV_SETTINGS \
"as=3\0" \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"rfsbargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rfsbpath}\0" \
"testrfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${testrfspath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw initrd=" \
"0x${ramdisk_addr_r},4M\0" \
"mtdids=nand0=davinci_nand.0\0" \
"serverip=192.168.5.249\0" \
"ipaddr=192.168.5.248\0" \
"rootpath=/opt/eldk/arm\0" \
"splashpos=230,180\0" \
"testrfspath=/opt/eldk/test_arm\0" \
"nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
"ubi.mtd=${as} root=ubi0:rootfs\0" \
"nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \
"ubi.mtd=${as} root=ubi0:rootfs\0" \
"addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=${consoledev},${baudrate}n8\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
"consoledev=ttyS0\0" \
"loadaddr=c0000014\0" \
"memory=32M\0" \
"kernel_addr_r=c0700000\0" \
"hostname=" CONFIG_HOSTNAME "\0" \
"bootfile=" CONFIG_HOSTNAME "/uImage\0" \
"ramdisk_file=" CONFIG_HOSTNAME "/image.ext2\0" \
"flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr_r}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr_r}\0" \
"net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
"run rfsbargs addip addtty addmtd addmisc addmem; " \
"bootm ${kernel_addr_r}\0" \
"net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run testrfsargs addip addtty addmtd addmisc addmem; " \
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
"nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"ubifsload ${kernel_addr_r} /boot/uImage;" \
"ubifsumount; run nandargs addip addtty " \
"addmtd addmisc addmem;clrlogo;" \
"bootm ${kernel_addr_r}\0" \
"nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"ubifsload ${kernel_addr_r} /boot/uImage;" \
"ubifsumount; run nandrwargs addip addtty " \
"addmtd addmisc addmem;clrlogo;" \
"bootm ${kernel_addr_r}\0" \
"net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
" addip addtty addmtd addmisc addmem;" \
"clrlogo;bootm ${kernel_addr_r}\0" \
"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"load_magic=if sf probe 0;then sf " \
"read c0000000 0x10000 0x60000;fi\0" \
"load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"if ubifsload c0000014 /boot/u-boot.bin;" \
"then mw c0000008 ${filesize};else echo Error reading" \
" u-boot from nand!;fi\0" \
"load_net=if sf probe 0;then sf read c0000000 0x10000 " \
"0x60000;tftp c0000014 ${u-boot};" \
"mw c0000008 ${filesize};fi\0" \
"upd=if sf probe 0;then sf erase 10000 60000;" \
"sf write c0000000 10000 60000;fi\0" \
"ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \
"sf erase 0 10000;" \
"sf write 0xc0700000 0 ${filesize};fi\0" \
"ubootupd_net=if run load_net;then echo Updating u-boot;" \
"if run upd; then echo U-Boot updated;" \
"else echo Error updating u-boot !;" \
"echo Board without bootloader !!;" \
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
"ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
"bootcmd=run net_testrfs\0"
#include <asm/arch/hardware.h>
#endif /* __CONFIG_H */

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include/configs/eco5pk.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 8D Technologies inc.
* Based on mt_ventoux.h, original banner below:
*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tam3517-common.h"
/* Our console port is port3 */
#undef CONFIG_SYS_NS16550_COM1
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_HOSTNAME "eco5pk"
/*
* Set its own mtdparts, different from common
*/
/*
* The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
*/
#undef CONFIG_ENV_OFFSET_REDUND
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"install_kernel=if dhcp $bootfile; then nand erase kernel;" \
"nand write $fileaddr kernel; fi\0" \
"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
"serverip=192.168.142.60\0"
#endif /* __CONFIG_H */

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include/configs/ipam390.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
* Based on:
* U-Boot:include/configs/da850evm.h
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Board
*/
/*
* SoC Configuration
*/
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
DAVINCI_SYSCFG_SUSPSRC_UART0 | \
DAVINCI_SYSCFG_SUSPSRC_EMAC)
/*
* PLL configuration
*/
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 24
/*
* DDR2 memory configuration
*/
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
(13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(2 << DV_DDR_SDTMR1_WR_SHIFT) | \
(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WTR_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
(2 << DV_DDR_SDCR_CL_SHIFT) | \
(3 << DV_DDR_SDCR_IBANK_SHIFT) | \
(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
DAVINCI_ABCR_WSTROBE(2) | \
DAVINCI_ABCR_WHOLD(0) | \
DAVINCI_ABCR_RSETUP(1) | \
DAVINCI_ABCR_RSTROBE(2) | \
DAVINCI_ABCR_RHOLD(1) | \
DAVINCI_ABCR_TA(0) | \
DAVINCI_ABCR_ASIZE_8BIT)
/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
/*
* Flash & Environment
*/
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
CONFIG_SYS_NAND_U_BOOT_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { \
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_LOAD
/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
/*
* U-Boot general configuration
*/
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_MX_CYCLIC
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
"root=/dev/mtdblock5 rw noinitrd " \
"rootfstype=jffs2 noinitrd\0" \
"hwconfig=dsp:wake=yes\0" \
"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
"bootfile=uImage\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"mtddevname=uboot-env\0" \
"mtddevnum=0\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"u-boot=/tftpboot/ipam390/u-boot.ais\0" \
"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
"nand write c0000000 20000 ${filesize}\0" \
"setbootparms=nand read c0100000 200000 400000;" \
"run defbootargs addmtd;" \
"spl export atags c0100000;" \
"nand erase.part bootparms;" \
"nand write c0000100 180000 20000\0" \
"\0"
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_MAX_FOOTPRINT 32768
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
/* add FALCON boot mode */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
/* GPIO support */
#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
#include <asm/arch/hardware.h>
#endif /* __CONFIG_H */

294
include/configs/mcx.h
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@ -1,294 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
*
* Based on omap3_evm_config.h
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
/*
* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
* and older u-boot.bin with the new U-Boot SPL.
*/
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
/*
* DDR related
*/
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
/* commands to include */
#define CONFIG_SYS_I2C
/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
/* Environment information */
#define CONFIG_BOOTFILE "uImage"
/* Setup MTD for NAND on the SOM */
#define CONFIG_HOSTNAME "mcx"
#define CONFIG_EXTRA_ENV_SETTINGS \
"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"addfb=setenv bootargs ${bootargs} vram=6M " \
"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
"addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:eth0:off\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"addtty=setenv bootargs ${bootargs} " \
"console=${consoledev},${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"baudrate=115200\0" \
"consoledev=ttyO2\0" \
"hostname=" CONFIG_HOSTNAME "\0" \
"loadaddr=0x82000000\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"load_k=tftp ${loadaddr} ${bootfile}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
"mlo=" CONFIG_HOSTNAME "/MLO\0" \
"mmcargs=root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"run addip addtty addmtd addfb addeth addmisc;" \
"run loaduimage; " \
"bootm ${loadaddr}\0" \
"net_nfs=run load_k; " \
"run nfsargs; " \
"run addip addtty addmtd addfb addeth addmisc;" \
"bootm ${loadaddr}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
"updatemlo=nandecc hw;nand erase 0 20000;" \
"nand write ${loadaddr} 0 20000\0" \
"upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \
"else echo Error updating u-boot !;" \
"echo Board without bootloader !!;" \
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"nandargs=setenv bootargs ubi.mtd=7 " \
"root=ubi0:rootfs rootfstype=ubifs\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"ubi part nand0,4;" \
"ubi readvol ${loadaddr} kernel;" \
"run addtty addmtd addfb addeth addmisc;" \
"bootm ${loadaddr}\0" \
"preboot=ubi part nand0,7;" \
"ubi readvol ${loadaddr} splash;" \
"bmp display ${loadaddr};" \
"gpio set 55\0" \
"swupdate_args=setenv bootargs root=/dev/ram " \
"quiet loglevel=1 " \
"consoleblank=0 ${swupdate_misc}\0" \
"swupdate=echo Running Sw-Update...;" \
"if printenv mtdparts;then echo Starting SwUpdate...; " \
"else mtdparts default;fi; " \
"ubi part nand0,5;" \
"ubi readvol 0x82000000 kernel_recovery;" \
"ubi part nand0,6;" \
"ubi readvol 0x84000000 fs_recovery;" \
"run swupdate_args; " \
"setenv bootargs ${bootargs} " \
"${mtdparts} " \
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
"omapdss.def_disp=lcd;" \
"bootm 0x82000000 0x84000000\0" \
"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
"then source 82000000;else run nandboot;fi\0"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
#define CONFIG_PREBOOT
/*
* AM3517 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*
* Physical Memory Map
*/
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET 0x180000
#define CONFIG_ENV_ADDR 0x180000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* Defines for SPL */
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/*
* ethernet support
*
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#endif /* __CONFIG_H */

46
include/configs/mt_ventoux.h
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@ -1,46 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
*
* Configuration settings for the Teejet mt_ventoux board.
*
* Copyright (C) 2009 TechNexion Ltd.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tam3517-common.h"
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
6 * 1024 * 1024)
#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_HOSTNAME "mt_ventoux"
/*
* Set its own mtdparts, different from common
*/
/*
* FPGA
*/
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 10000
#define CONFIG_MAX_FPGA_DEVICES 1
#define CONFIG_FPGA_DELAY() udelay(1)
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run net_nfs\0"
#endif /* __CONFIG_H */

34
include/configs/twister.h
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@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*
* Configuration for the Technexion twister board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tam3517-common.h"
#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
#define CONFIG_TAM3517_SW3_SETTINGS
#define CONFIG_XR16L2751
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_HOSTNAME "twister"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run nandboot\0"
/* SPL OS boot options */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#endif /* __CONFIG_H */

18
include/led-display.h
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@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2005-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*/
#ifndef _led_display_h_
#define _led_display_h_
/* Display Commands */
#define DISPLAY_CLEAR 0x1 /* Clear the display */
#define DISPLAY_HOME 0x2 /* Set cursor at home position */
void display_set(int cmd);
int display_putc(char c);
#endif

1
scripts/config_whitelist.txt
View File

@ -218,7 +218,6 @@ CONFIG_CM_MULTIPLE_SSRAM
CONFIG_CM_REMAP
CONFIG_CM_SPD_DETECT
CONFIG_CM_T335
CONFIG_CM_T3517
CONFIG_CM_T3X
CONFIG_CM_T43
CONFIG_CM_T54