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x86: Update device tree for TPL 

Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-05-02 10:52:19 -06:00 committed by Bin Meng
parent d4d2521c06
commit 93c7607580
1 changed files with 32 additions and 2 deletions
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34
arch/x86/dts/u-boot.dtsi
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@ -22,7 +22,21 @@
filename = CONFIG_INTEL_ME_FILE; filename = CONFIG_INTEL_ME_FILE;
}; };
#endif #endif
#ifdef CONFIG_SPL #ifdef CONFIG_TPL
u-boot-tpl-with-ucode-ptr {
offset = <CONFIG_TPL_TEXT_BASE>;
};
u-boot-tpl-dtb {
};
u-boot-spl {
offset = <CONFIG_SPL_TEXT_BASE>;
};
u-boot-spl-dtb {
};
u-boot {
offset = <CONFIG_SYS_TEXT_BASE>;
};
#elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr { u-boot-spl-with-ucode-ptr {
offset = <CONFIG_SPL_TEXT_BASE>; offset = <CONFIG_SPL_TEXT_BASE>;
}; };
@ -31,7 +45,19 @@
type = "u-boot-dtb-with-ucode"; type = "u-boot-dtb-with-ucode";
}; };
u-boot { u-boot {
/*
* TODO(sjg@chromium.org):
* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
* for boards with textbase in SDRAM we cannot do this. Just use
* an assumed-valid value (1MB before the end of flash) here so
* that we can actually build an image for coreboot, etc.
* We need a better solution, perhaps a separate Kconfig.
*/
#if CONFIG_SYS_TEXT_BASE == 0x1110000
offset = <0xfff00000>; offset = <0xfff00000>;
#else
offset = <CONFIG_SYS_TEXT_BASE>;
#endif
}; };
#else #else
u-boot-with-ucode-ptr { u-boot-with-ucode-ptr {
@ -77,7 +103,11 @@
offset = <CONFIG_X86_REFCODE_ADDR>; offset = <CONFIG_X86_REFCODE_ADDR>;
}; };
#endif #endif
#ifdef CONFIG_SPL #ifdef CONFIG_TPL
x86-start16-tpl {
offset = <CONFIG_SYS_X86_START16>;
};
#elif defined(CONFIG_SPL)
x86-start16-spl { x86-start16-spl {
offset = <CONFIG_SYS_X86_START16>; offset = <CONFIG_SYS_X86_START16>;
}; };