FIX: [uboot] Fix RAM timings, dynamic clk detection

Fix the RAM timings for 512MB, the old timings were for 256MB only, the new ones should work for
both sizes.
Detect the Oszillator clock based on the sysboot1 settings, this is necessary because old Prototypes
(series 1) have a 24 MHz clock and the new ones have a 25 MHz clock.

SVN commit 21612@trunk

arch/arm/cpu/armv7/am33xx/clock_am33xx.c

@@ -21,6 +21,8 @@ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
+struct ctrl_stat *const ctrlstat = (struct ctrl_stat*)CTRL_BASE;
+
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x88,
 	.cm_idlest_dpll		= CM_WKUP + 0x20,
@@ -53,13 +55,13 @@ const struct dpll_regs dpll_ddr_regs = {
 
 struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core_opp100 = {
+struct dpll_params dpll_core_opp100 = {
-		1000, OSC-1, -1, -1, 10, 8, 4};
+  1000, OSC-1, -1, -1, 10, 8, 4};
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu = {
-		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+  MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+struct dpll_params dpll_core = {
-		50, OSC-1, -1, -1, 1, 1, 1};
+  50, OSC-1, -1, -1, 1, 1, 1};
-const struct dpll_params dpll_per = {
+struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
 const struct dpll_params *get_dpll_mpu_params(void)
@@ -113,8 +115,25 @@ void setup_clocks_for_console(void)
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
+static inline unsigned long get_osclk_dpll(void)
+{
+	return (get_osclk() / 1000000) - 1;
+}
+
+static inline void am33xx_init_osc_clock(void)
+{
+	unsigned long n = get_osclk_dpll();
+	dpll_mpu_opp100.n = n;
+	dpll_core_opp100.n = n;
+	dpll_mpu.n = n;
+	dpll_core.n = n;
+	dpll_per.n = n;
+}
+
 void enable_basic_clocks(void)
 {
+	am33xx_init_osc_clock();
+
 	u32 *const clk_domains[] = {
 		&cmper->l3clkstctrl,
 		&cmper->l4fwclkstctrl,
@@ -159,3 +178,18 @@ void enable_basic_clocks(void)
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
 }
+
+static unsigned long ram_timings[] = {
+	19200000, 24000000, 25000000, 26000000
+};
+
+unsigned long get_osclk(void)
+{
+	if (V_OSCK != 0) {
+		return V_OSCK;
+	}
+	else {
+		unsigned int sysboot1 = (readl(&ctrlstat->statusreg) >> 22) & 3;
+		return ram_timings[sysboot1];
+	}
+}

arch/arm/cpu/armv7/omap-common/abb.c

@@ -48,7 +48,7 @@ static void abb_setup_timings(u32 setup)
 	 */
 
 	/* calculate SR2_WTCNT_VALUE */
-	sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+	sys_rate = DIV_ROUND_CLOSEST(get_osclk(), 1000000);
 	clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
 	sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
 

arch/arm/cpu/armv7/omap-common/timer.c

@@ -33,6 +33,16 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 #define TIMER_OVERFLOW_VAL	0xffffffff
 #define TIMER_LOAD_VAL		0
 
+static inline unsigned long get_timer_clock(void)
+{
+	if (V_SCLK != 0) {
+		return TIMER_CLOCK;
+	}
+	else {
+		return get_osclk() / (2 << CONFIG_SYS_PTV);
+	}
+}
+
 int timer_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
@@ -55,7 +65,7 @@ ulong get_timer(ulong base)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	long tmo = usec * (get_timer_clock() / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 
 	while (tmo > 0) {
@@ -71,13 +81,13 @@ void __udelay(unsigned long usec)
 ulong get_timer_masked(void)
 {
 	/* current tick value */
-	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	ulong now = readl(&timer_base->tcrr) / (get_timer_clock() / CONFIG_SYS_HZ);
 
 	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
 		gd->arch.tbl += (now - gd->arch.lastinc);
 	} else {	/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (get_timer_clock() /
 				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
 	}
 	gd->arch.lastinc = now;

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h

@@ -32,7 +32,8 @@
 #define CM_DLL_READYST		0x4
 
 extern void enable_dmm_clocks(void);
-extern const struct dpll_params dpll_core_opp100;
+extern unsigned long get_osclk(void);
+extern struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */

board/nm/netbird/board.c

@@ -59,6 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define NETBIRD_GPIO_LED_B		GPIO_TO_PIN(1, 15)
 #define NETBIRD_GPIO_RESET_BUTTON	GPIO_TO_PIN(1, 13)
 
+#define DDR3_CLOCK_FREQUENCY (400)
+
 #if defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
@@ -100,10 +102,10 @@ static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
 
 static struct emif_regs ddr3_netbird_emif_reg_data = {
 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
-	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.ref_ctrl = 0x61A,	/* 32ms > 85°C */
-	.sdram_tim1 = 0x0aaae51b, /* From AM335x_DDR_register_calc_tool.xls */
+	.sdram_tim1 = 0x0AAAE51B,
-	.sdram_tim2 = 0x24437fda, /* From AM335x_DDR_register_calc_tool.xls */
+	.sdram_tim2 = 0x246B7FDA,
-	.sdram_tim3 = 0x50ffe3ff, /* From AM335x_DDR_register_calc_tool.xls */
+	.sdram_tim3 = 0x50FFE67F,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
@@ -128,8 +130,8 @@ int spl_start_uboot(void)
 #endif
 
 #define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr_nbhw16= {
+struct dpll_params dpll_ddr_nbhw16= {
-		400, OSC-1, 1, -1, -1, -1, -1};
+		DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1};
 
 void am33xx_spl_board_init(void)
 {
@@ -156,6 +158,7 @@ void am33xx_spl_board_init(void)
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
+	dpll_ddr_nbhw16.n = (get_osclk() / 1000000) - 1;
 	return &dpll_ddr_nbhw16;
 }
 
@@ -181,13 +184,13 @@ const struct ctrl_ioregs ioregs_netbird = {
 
 void sdram_init(void)
 {
-	config_ddr(400, &ioregs_netbird,
+	config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
 		   &ddr3_netbird_data,
 		   &ddr3_netbird_cmd_ctrl_data,
 		   &ddr3_netbird_emif_reg_data, 0);
 }
 
-#endif
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 static void request_and_set_gpio(int gpio, char *name, int value)
 {
@@ -346,6 +349,8 @@ int board_init(void)
 	#define SMA2_REGISTER (CTRL_BASE + 0x1320)
 	writel(0x01, SMA2_REGISTER); /* Select RMII2_CRS_DV instead of MMC2_DAT7 */
 
+	printf("OSC: %lu Hz\n", get_osclk());
+
 	return 0;
 }
 

include/configs/am335x_netbird.h

@@ -39,7 +39,7 @@
 #define CONFIG_BOARD_LATE_INIT
 
 /* Clock Defines */
-#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_OSCK				0 /* 0 means detect from sysboot1 config */
 #define V_SCLK				(V_OSCK)
 
 #include <config_distro_bootcmd.h>