* Fix PCI support for MPC5200 / IceCube Board
This commit is contained in:
wdenk
parent
bdccc4fedc
commit
96e48cf6c1
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@ -2,6 +2,8 @@
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Changes for U-Boot 0.4.5:
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======================================================================
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* Fix PCI support for MPC5200 / IceCube Board
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* Map ISP1362 USB OTG controller for NSCU board
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* Patch by Brad Parker, 02 Aug 2003:
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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long int initdram (int board_type)
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{
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@ -114,3 +115,14 @@ void flash_preinit(void)
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#endif
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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@ -28,7 +28,7 @@ LIB = lib$(CPU).a
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START = start.o
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ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
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OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
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loadtask.o fec.o
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loadtask.o fec.o pci_mpc5200.o
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all: .depend $(START) $(ASOBJS) $(LIB)
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@ -0,0 +1,175 @@
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <mpc5xxx.h>
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/* System RAM mapped over PCI */
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#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
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#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
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/* PCIIWCR bit fields */
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#define IWCR_MEM (0 << 3)
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#define IWCR_IO (1 << 3)
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#define IWCR_READ (0 << 1)
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#define IWCR_READLINE (1 << 1)
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#define IWCR_READMULT (2 << 1)
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#define IWCR_EN (1 << 0)
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static int mpc5200_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32* value)
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{
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*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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eieio();
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*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
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eieio();
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*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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/* skip MPC5200 */
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if (offset == 0 && *value == 0x58031057)
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*value = 0xffffffff;
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return 0;
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}
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static int mpc5200_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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eieio();
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out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
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eieio();
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*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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return 0;
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}
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void pci_mpc5xxx_init (struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEMORY_BUS,
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CONFIG_PCI_MEMORY_PHYS,
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CONFIG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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pci_register_hose(hose);
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/* GPIO Multiplexing - enable PCI */
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
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/* Set host bridge as pci master and enable memory decoding */
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*(vu_long *)MPC5XXX_PCI_CMD |=
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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/* Set maximum latency timer */
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*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
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/* Set cache line size */
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*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
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(CFG_CACHELINE_SIZE / 4);
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/* Map MBAR to PCI space */
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*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
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*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
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/* Map RAM to PCI space */
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*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
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*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
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/* Enable snooping for RAM */
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*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
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*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
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/* Park XLB on PCI */
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*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
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*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
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/* Enable piplining */
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*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
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/* Disable interrupts from PCI controller */
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*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
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*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
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/* Disable initiator windows */
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*(vu_long *)MPC5XXX_PCI_IWCR = 0;
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/* Map PCI memory to physical space */
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*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
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(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
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(CONFIG_PCI_MEM_BUS >> 16);
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*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
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/* Map PCI I/O to physical space */
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*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
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(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
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(CONFIG_PCI_IO_BUS >> 16);
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*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
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/* Reset the PCI bus */
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*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
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udelay(1000);
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*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
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udelay(1000);
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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mpc5200_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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mpc5200_write_config_dword);
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udelay(1000);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI && CONFIG_MPC5200 */
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@ -37,7 +37,7 @@
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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@ -49,10 +49,41 @@
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_NET_MULTI 1
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#define CONFIG_EEPRO100 1
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define ADD_PCI_CMD CFG_CMD_PCI
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#else /* MPC5100 */
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#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
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#endif
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS CONFIG_CMD_DFL
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@ -93,7 +124,7 @@
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#define CFG_ENV_SIZE 0x10000
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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@ -61,6 +61,10 @@
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#if defined(CONFIG_MGT5100)
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#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
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#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
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#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
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#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
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#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
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#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
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#elif defined(CONFIG_MPC5200)
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#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
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#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
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@ -75,6 +79,7 @@
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#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
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#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
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#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
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#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
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#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
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#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
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@ -136,6 +141,33 @@
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/* GPIO registers */
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#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
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/* PCI registers */
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#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
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#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
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#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
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#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
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#if defined(CONFIG_MGT5100)
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#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
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#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
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#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
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#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
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#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
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#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
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#elif defined(CONFIG_MPC5200)
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#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
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#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
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#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
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#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
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#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
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#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
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#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
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#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
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#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
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#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
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#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
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#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
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#endif
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/* Interrupt Controller registers */
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#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
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#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
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