LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm: dts: k3-am68-sk: Add support for OSPI Flash 

AM68 SK has an OSPI NOR flash on its SOM which is connected to the MCU
OSPI0 instance. Add support for the same and enable it in SPL and
U-Boot.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
This commit is contained in:
Sinthu Raja 2023-07-05 16:16:45 +05:30 committed by Udit Kumar
parent ad94285326
commit 9878ad5c08
3 changed files with 109 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
View File

@ -21,6 +21,7 @@
i2c3 = &main_i2c0; i2c3 = &main_i2c0;
ethernet0 = &cpsw_port1; ethernet0 = &cpsw_port1;
mmc1 = &main_sdhci1; mmc1 = &main_sdhci1;
spi0 = &ospi0;
}; };
}; };
@ -156,6 +157,30 @@
}; };
}; };
&fss {
bootph-pre-ram;
};
&mcu_fss0_ospi0_pins_default {
bootph-pre-ram;
};
&ospi0 {
bootph-pre-ram;
ospi0_nor: flash@0 {
bootph-pre-ram;
partition@3fc0000 {
bootph-pre-ram;
};
};
};
&ospi0_nor {
bootph-pre-ram;
};
&serdes_ln_ctrl { &serdes_ln_ctrl {
u-boot,mux-autoprobe; u-boot,mux-autoprobe;
}; };

5
arch/arm/dts/k3-am68-sk-r5-base-board.dts
View File

@ -191,4 +191,9 @@
ti,sci = <&dm_tifs>; ti,sci = <&dm_tifs>;
}; };
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
#include "k3-am68-sk-base-board-u-boot.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi"

79
arch/arm/dts/k3-am68-sk-som.dtsi
View File

@ -30,6 +30,85 @@
}; };
}; };
&wkup_pmx0 {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
ospi0_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster0 { &mailbox0_cluster0 {
status = "disabled"; status = "disabled";
}; };