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Merge git://www.denx.de/git/u-boot-marvell

This commit is contained in:
Tom Rini 2016-10-12 08:30:08 -04:00
parent 711b534120 1c653201d7
commit 99615d812f
10 changed files with 637 additions and 0 deletions
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4
arch/arm/mach-kirkwood/Kconfig
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@ -10,6 +10,9 @@ config TARGET_OPENRD
config TARGET_DREAMPLUG
bool "DreamPlug Board"
config TARGET_DS109
bool "Synology DS109"
config TARGET_GURUPLUG
bool "GuruPlug Board"
@ -59,6 +62,7 @@ config SYS_SOC
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Synology/ds109/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"

12
board/Synology/ds109/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_DS109
config SYS_BOARD
default "ds109"
config SYS_VENDOR
default "Synology"
config SYS_CONFIG_NAME
default "ds109"
endif

6
board/Synology/ds109/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
DS109 BOARD
M: Walter Schweizer <swwa@users.sourceforge.net>
S: Maintained
F: board/Synology/ds109
F: configs/ds109_defconfig
F: include/configs/ds109.h

9
board/Synology/ds109/Makefile Normal file
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@ -0,0 +1,9 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ds109.o

176
board/Synology/ds109/ds109.c Normal file
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@ -0,0 +1,176 @@
/*
* Copyright (C) 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <luka@openwrt.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include "ds109.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
mvebu_config_gpio(DS109_OE_VAL_LOW,
DS109_OE_VAL_HIGH,
DS109_OE_LOW, DS109_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
MPP0_SPI_SCn, /* SPI Flash */
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP4_GPIO,
MPP5_GPO,
MPP6_SYSRST_OUTn, /* Reset signal */
MPP7_GPO,
MPP8_TW_SDA, /* I2C */
MPP9_TW_SCK, /* I2C */
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO,
MPP13_UART1_TXD,
MPP14_UART1_RXD,
MPP15_GPIO,
MPP16_GPIO,
MPP17_GPIO,
MPP18_GPO,
MPP19_GPO,
MPP20_SATA1_ACTn,
MPP21_SATA0_ACTn,
MPP22_GPIO, /* HDD2 FAIL LED */
MPP23_GPIO, /* HDD1 FAIL LED */
MPP24_GPIO,
MPP25_GPIO,
MPP26_GPIO,
MPP27_GPIO,
MPP28_GPIO,
MPP29_GPIO,
MPP30_GPIO,
MPP31_GPIO, /* HDD2 */
MPP32_GPIO, /* FAN A */
MPP33_GPIO, /* FAN B */
MPP34_GPIO, /* FAN C */
MPP35_GPIO, /* FAN SENSE */
MPP36_GPIO,
MPP37_GPIO,
MPP38_GPIO,
MPP39_GPIO,
MPP40_GPIO,
MPP41_GPIO,
MPP42_GPIO,
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
MPP46_GPIO,
MPP47_GPIO,
MPP48_GPIO,
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
/* Synology reset uses UART */
#include <ns16550.h>
#define SOFTWARE_SHUTDOWN 0x31
#define SOFTWARE_REBOOT 0x43
#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
void reset_misc(void)
{
int b_d;
printf("Synology reset...");
udelay(50000);
b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
CONFIG_SYS_NS16550_CLK, 9600);
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
}
/* Support old kernels */
void setup_board_tags(struct tag **in_params)
{
unsigned int boardId;
struct tag *params;
struct tag_mv_uboot *t;
int i;
printf("Synology board tags...");
params = *in_params;
t = (struct tag_mv_uboot *)&params->u;
t->uboot_version = VER_NUM;
boardId = SYNO_DS109_ID;
t->uboot_version |= boardId;
t->tclk = CONFIG_SYS_TCLK;
t->sysclk = CONFIG_SYS_TCLK*2;
t->isusbhost = 1;
for (i = 0; i < 4; i++) {
memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
t->mtu[i] = 0;
}
params->hdr.tag = ATAG_MV_UBOOT;
params->hdr.size = tag_size(tag_mv_uboot);
params = tag_next(params);
*in_params = params;
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
printf("Error: 88E1116 could not read PHY dev address\n");
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */

44
board/Synology/ds109/ds109.h Normal file
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@ -0,0 +1,44 @@
/*
* Copyright (C) 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <luka@openwrt.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DS109_H
#define __DS109_H
#define DS109_OE_LOW (0)
#define DS109_OE_HIGH (0)
#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23))
#define DS109_OE_VAL_HIGH ((1 << 1)|1)
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_MAC_CTRL2_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
/* Marvell uboot parameters */
#define ATAG_MV_UBOOT 0x41000403
#define VER_NUM 0x03040400 /* 3.4.4 */
#define BOARD_ID_BASE 0x0
#define SYNO_DS109_ID (BOARD_ID_BASE+0x15)
struct tag_mv_uboot {
u32 uboot_version;
u32 tclk;
u32 sysclk;
u32 isusbhost;
char macaddr[4][6];
u16 mtu[4];
u32 fw_image_base;
u32 fw_image_size;
};
#endif /* __DS109_H */

152
board/Synology/ds109/kwbimage.cfg Normal file
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@ -0,0 +1,152 @@
#
# (C) Copyright 2011
# Jason Cooper <u-boot@lakedaemon.net>
#
# Based on work by:
# Marvell Semiconductor <www.marvell.com>
# Written-by: Siddarth Gore <gores@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0/1 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
DATA 0xFFD20134 0xbbbbbbbb
DATA 0xFFD20138 0x00bbbbbb
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x0000000d # DDR Address Control
# bit1-0: 01, Cs0width=x8
# bit3-2: 10, Cs0size=1Gb
# bit5-4: 01, Cs1width=x8
# bit7-6: 10, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000042 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

115
board/Synology/ds109/openocd.cfg Normal file
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@ -0,0 +1,115 @@
# Synology DS109
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x000b
ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
adapter_khz 2000
# length of reset signal: [ms]
adapter_nsrst_assert_width 1000
# don't talk to JTAG after reset for: [ms]
adapter_nsrst_delay 200
source [find target/feroceon.cfg]
reset_config trst_and_srst srst_nogate
proc ds109_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
#reset run
#soft_reset_halt
arm mcr 15 0 0 1 0 0x00052078
mww 0xD00100e0 0x1b1b1b9b ;#
mww 0xD0020134 0xbbbbbbbb ;#
mww 0xD0020138 0x00bbbbbb ;#
mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
mww 0xD0001428 0x00085520 ;# Dunit Control High Register
mww 0xD000147c 0x00008552 ;# Dunit Control High Register
mww 0xD0001500 0x00000000 ;#
mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
mww 0xD0001508 0x10000000 ;# CS1n Base Register
mww 0xD000150C 0x00000000 ;# CS1n Size Register
mww 0xD0001510 0x20000000 ;#
mww 0xD0001514 0x00000000 ;# CS2n Size Register
mww 0xD000151C 0x00000000 ;# CS3n Size Register
mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0010000 0x01111111 ;# MPP 0 to 7
mww 0xD0010004 0x11113322 ;# MPP 8 to 15
mww 0xD0010008 0x00001111 ;# MPP 16 to 23
}
proc ds109_load { } {
# load u-Boot into RAM and execute it
ds109_init
load_image u-boot.bin 0x00600000 bin
resume 0x00600000
}

16
configs/ds109_defconfig Normal file
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@ -0,0 +1,16 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DS109=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y

103
include/configs/ds109.h Normal file
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@ -0,0 +1,103 @@
/*
* (C) Copyright 2011
* Jason Cooper <u-boot@lakedaemon.net>
*
* Based on work by:
* Marvell Semiconductor <www.marvell.com>
* Written-by: Siddarth Gore <gores@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_DS109_H
#define _CONFIG_DS109_H
/*
* FIXME: This belongs in mach-types.h. However, we only pull mach-types
* from Linus' kernel.org tree. This hasn't been updated primarily due to
* the recent arch/arm reshuffling. So, in the meantime, we'll place it
* here.
*/
#include <asm/mach-types.h>
#ifdef MACH_TYPE_SYNOLOGY
#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this."
#else
#define MACH_TYPE_SYNOLOGY 527
#endif
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY
/*
* Commands configuration
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/*
* mv-plug-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-plug-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_ADDR 0x3d0000
#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.1.2\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \
"ipaddr=192.168.1.5\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
#define CONFIG_PHY_BASE_ADR 8
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_DS109_H */