ENGR00315894-78 vadc: Add vadc module
Add vadc module. Both PAL and NTSC mode can work. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 03c31ae30c1e81c99f6824221e4801433445e04a) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b5d776ffc1519c16091736445b3217ffb7fcd7db) (cherry picked from commit 2377eb9fd299b76888f11faf76383b68e77bcc8a) (cherry picked from commit 808d447235bd0f9134c7d00fa480cd55b4e0426e)
This commit is contained in:
Ye.Li
Ye Li
parent
e0cfa88953
commit
99977a1152
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/string.h>
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#include <linux/list.h>
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#include <gis.h>
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#include "mxc_vadc.h"
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#define reg32_write(addr, val) __raw_writel(val, addr)
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#define reg32_read(addr) __raw_readl(addr)
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#define reg32setbit(addr, bitpos) \
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reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
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#define reg32clrbit(addr, bitpos) \
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reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
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void __iomem *vafe_regbase;
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void __iomem *vdec_regbase;
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enum {
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STD_NTSC = 0,
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STD_PAL,
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};
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/* Video format structure. */
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struct video_fmt_t{
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int v4l2_id; /* Video for linux ID. */
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char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */
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u16 active_width; /* Active width. */
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u16 active_height; /* Active height. */
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};
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/* Description of video formats supported.
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*
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* PAL: active=720x576.
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* NTSC:active=720x480.
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*/
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static struct video_fmt_t video_fmts[] = {
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/* NTSC */
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{
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.v4l2_id = STD_NTSC,
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.name = "NTSC",
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.active_width = 720,
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.active_height = 480,
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},
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/* (B, G, H, I, N) PAL */
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{
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.v4l2_id = STD_PAL,
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.name = "PAL",
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.active_width = 720,
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.active_height = 576,
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},
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};
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static void afe_voltage_clampingmode(void)
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{
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reg32_write(AFE_CLAMP, 0x07);
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reg32_write(AFE_CLMPAMP, 0x60);
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reg32_write(AFE_CLMPDAT, 0xF0);
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}
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static void afe_alwayson_clampingmode(void)
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{
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reg32_write(AFE_CLAMP, 0x15);
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reg32_write(AFE_CLMPDAT, 0x08);
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reg32_write(AFE_CLMPAMP, 0x00);
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}
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static void afe_init(void)
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{
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reg32_write(AFE_PDBUF, 0x1f);
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reg32_write(AFE_PDADC, 0x0f);
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reg32_write(AFE_PDSARH, 0x01);
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reg32_write(AFE_PDSARL, 0xff);
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reg32_write(AFE_PDADCRFH, 0x01);
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reg32_write(AFE_PDADCRFL, 0xff);
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reg32_write(AFE_ICTRL, 0x3a);
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reg32_write(AFE_ICTLSTG, 0x1e);
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reg32_write(AFE_RCTRLSTG, 0x1e);
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reg32_write(AFE_INPBUF, 0x035);
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reg32_write(AFE_INPFLT, 0x02);
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reg32_write(AFE_ADCDGN, 0x40);
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reg32_write(AFE_TSTSEL, 0x10);
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reg32_write(AFE_ACCTST, 0x07);
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reg32_write(AFE_BGREG, 0x08);
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reg32_write(AFE_ADCGN, 0x09);
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/* set current controlled clamping
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* always on, low current */
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reg32_write(AFE_CLAMP, 0x11);
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reg32_write(AFE_CLMPAMP, 0x08);
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}
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static void vdec_mode_timing_init(u32 std)
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{
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if (std == STD_NTSC) {
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/* NTSC 720x480 */
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printf("NTSC\n");
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reg32_write(VDEC_HACTS, 0x66);
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reg32_write(VDEC_HACTE, 0x24);
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reg32_write(VDEC_VACTS, 0x29);
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reg32_write(VDEC_VACTE, 0x04);
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/* set V Position */
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reg32_write(VDEC_VRTPOS, 0x2);
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} else if (std == STD_PAL) {
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/* PAL 720x576 */
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printf("PAL\n");
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reg32_write(VDEC_HACTS, 0x66);
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reg32_write(VDEC_HACTE, 0x24);
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reg32_write(VDEC_VACTS, 0x29);
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reg32_write(VDEC_VACTE, 0x04);
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/* set V Position */
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reg32_write(VDEC_VRTPOS, 0x6);
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} else
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printf("Error not support video mode\n");
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/* set H Position */
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reg32_write(VDEC_HZPOS, 0x60);
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/* set H ignore start */
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reg32_write(VDEC_HSIGS, 0xf8);
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/* set H ignore end */
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reg32_write(VDEC_HSIGE, 0x18);
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}
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/*
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* vdec_init()
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* Initialises the VDEC registers
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* Returns: nothing
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*/
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static void vdec_init(struct sensor_data *vadc)
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{
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/* Get work mode PAL or NTSC
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* delay 500ms wait vdec detect input format*/
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udelay(500*1000);
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vadc_get_std(vadc);
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vdec_mode_timing_init(vadc->std_id);
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/* vcr detect threshold high, automatic detections */
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reg32_write(VDEC_VSCON2, 0);
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reg32_write(VDEC_BASE + 0x110, 0x01);
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/* set the noramp mode on the Hloop PLL. */
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reg32_write(VDEC_BASE+(0x14*4), 0x10);
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/* set the YC relative delay.*/
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reg32_write(VDEC_YCDEL, 0x90);
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/* setup the Hpll */
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reg32_write(VDEC_BASE+(0x13*4), 0x13);
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/* setup the 2d comb */
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/* set the gain of the Hdetail output to 3
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* set the notch alpha gain to 1 */
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reg32_write(VDEC_CFC2, 0x34);
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/* setup various 2d comb bits.*/
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reg32_write(VDEC_BASE+(0x02*4), 0x01);
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reg32_write(VDEC_BASE+(0x03*4), 0x18);
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reg32_write(VDEC_BASE+(0x04*4), 0x34);
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/* set the start of the burst gate */
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reg32_write(VDEC_BRSTGT, 0x30);
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/* set 1f motion gain */
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reg32_write(VDEC_BASE+(0x0f*4), 0x20);
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/* set the 1F chroma motion detector thresh for colour reverse detection */
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reg32_write(VDEC_THSH1, 0x02);
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reg32_write(VDEC_BASE+(0x4a*4), 0x20);
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reg32_write(VDEC_BASE+(0x4b*4), 0x08);
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reg32_write(VDEC_BASE+(0x4c*4), 0x08);
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/* set the threshold for the narrow/wide adaptive chroma BW */
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reg32_write(VDEC_BASE+(0x20*4), 0x20);
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/* turn up the colour with the new colour gain reg */
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/* hue: */
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reg32_write(VDEC_HUE, 0x00);
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/* cbgain: 22 B4 */
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reg32_write(VDEC_CBGN, 0xb4);
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/* cr gain 80 */
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reg32_write(VDEC_CRGN, 0x80);
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/* luma gain (contrast) */
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reg32_write(VDEC_CNTR, 0x80);
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/* setup the signed black level register, brightness */
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reg32_write(VDEC_BRT, 0x00);
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/* filter the standard detection
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* enable the comb for the ntsc443 */
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reg32_write(VDEC_STDDBG, 0x23);
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/* setup chroma kill thresh for no chroma */
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reg32_write(VDEC_CHBTH, 0x0);
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/* set chroma loop to wider BW
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* no set it to normal BW. i fixed the bw problem.*/
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reg32_write(VDEC_YCDEL, 0x00);
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/* set the compensation in the chroma loop for the Hloop
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* set the ratio for the nonarithmetic 3d comb modes.*/
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reg32_write(VDEC_BASE + (0x1d*4), 0x90);
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/* set the threshold for the nonarithmetic mode for the 2d comb
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* the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */
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reg32_write(VDEC_BASE + (0x33*4), 0xa0);
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/* setup the bluescreen output colour */
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reg32_write(VDEC_BASE + (0x3d*4), 35);
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reg32_write(VDEC_BLSCRCR, 114);
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reg32_write(VDEC_BLSCRCB, 212);
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/* disable the active blanking */
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reg32_write(VDEC_BASE + (0x15*4), 0x02);
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/* setup the luma agc for automatic gain. */
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reg32_write(VDEC_LMAGC2, 0x5e);
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reg32_write(VDEC_BASE + (0x40*4), 0x81);
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/* setup chroma agc */
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reg32_write(VDEC_CHAGC2, 0xa0);
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reg32_write(VDEC_CHAGC1, 0x01);
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/* setup the MV thresh lower nibble
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* setup the sync top cap, upper nibble */
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reg32_write(VDEC_BASE + (0x3a*4), 0x80);
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reg32_write(VDEC_SHPIMP, 0x00);
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/* setup the vsync block */
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reg32_write(VDEC_VSCON1, 0x87);
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/* set the nosignal threshold
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* set the vsync threshold */
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reg32_write(VDEC_VSSGTH, 0x35);
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/* set length for min hphase filter (or saturate limit if saturate is chosen) */
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reg32_write(VDEC_BASE + (0x45*4), 0x40);
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/* enable the internal resampler,
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* select min filter not saturate for hphase noise filter for vcr detect.
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* enable vcr pause mode different field lengths */
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reg32_write(VDEC_BASE + (0x46*4), 0x90);
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/* disable VCR detection, lock to the Hsync rather than the Vsync */
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reg32_write(VDEC_VSCON2, 0x04);
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/* set tiplevel goal for dc clamp. */
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reg32_write(VDEC_BASE + (0x3c*4), 0xB0);
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/* override SECAM detection and force SECAM off */
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reg32_write(VDEC_BASE + (0x2f*4), 0x20);
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/* Set r3d_hardblend in 3D control2 reg */
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reg32_write(VDEC_BASE + (0x0c*4), 0x04);
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}
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/* set Input selector & input pull-downs */
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static void vadc_select_input(int vadc_in)
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{
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switch (vadc_in) {
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case 0:
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reg32_write(AFE_INPFLT, 0x02);
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reg32_write(AFE_OFFDRV, 0x00);
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reg32_write(AFE_INPCONFIG, 0x1e);
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break;
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case 1:
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reg32_write(AFE_INPFLT, 0x02);
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reg32_write(AFE_OFFDRV, 0x00);
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reg32_write(AFE_INPCONFIG, 0x2d);
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break;
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case 2:
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reg32_write(AFE_INPFLT, 0x02);
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reg32_write(AFE_OFFDRV, 0x00);
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reg32_write(AFE_INPCONFIG, 0x4b);
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break;
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case 3:
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reg32_write(AFE_INPFLT, 0x02);
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reg32_write(AFE_OFFDRV, 0x00);
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reg32_write(AFE_INPCONFIG, 0x87);
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break;
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default:
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printf("error video input %d\n", vadc_in);
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}
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}
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/*!
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* Return attributes of current video standard.
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* Since this device autodetects the current standard, this function also
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* sets the values that need to be changed if the standard changes.
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* There is no set std equivalent function.
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*
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* @return None.
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*/
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void vadc_get_std(struct sensor_data *vadc)
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{
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int tmp;
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int idx;
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/* Read PAL mode detected result */
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tmp = reg32_read(VDEC_VIDMOD);
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tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK);
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if (tmp)
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idx = STD_PAL;
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else
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idx = STD_NTSC;
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vadc->std_id = idx;
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vadc->pixel_fmt = FMT_YUV444;
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vadc->width = video_fmts[idx].active_width;
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vadc->height = video_fmts[idx].active_height;
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}
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void vadc_config(u32 vadc_in)
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{
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struct sensor_data vadc;
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/* map vafe,vdec,gpr,gpc address */
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vafe_regbase = (u32 *)VADC_BASE_ADDR;
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vdec_regbase = (u32 *)VDEC_BASE_ADDR;
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vadc_power_up();
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/* clock config for vadc */
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reg32_write(VDEC_BASE + 0x320, 0xe3);
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reg32_write(VDEC_BASE + 0x324, 0x38);
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reg32_write(VDEC_BASE + 0x328, 0x8e);
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reg32_write(VDEC_BASE + 0x32c, 0x23);
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mxs_set_vadcclk();
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afe_init();
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/* select Video Input 0-3 */
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vadc_select_input(vadc_in);
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afe_voltage_clampingmode();
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vdec_init(&vadc);
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/*
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* current control loop will move sinewave input off below
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* the bottom of the signal range visible when the testbus is viewed as magnitude,
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* so have to break before this point while capturing ENOB data:
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*/
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afe_alwayson_clampingmode();
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}
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@ -0,0 +1,230 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef MXC_VADC_H
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#define MXC_VADC_H
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/*** define base address ***/
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#define VDEC_BASE vdec_regbase
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#define AFE_BASE vafe_regbase
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/* AFE - Register offsets */
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#define AFE_BLOCK_ID_OFFSET 0x00000000
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#define AFE_PDBUF_OFFSET 0x00000004
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#define AFE_SWRST_OFFSET 0x00000008
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#define AFE_TSTSEL_OFFSET 0x0000000c
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#define AFE_TSTMSC_OFFSET 0x00000010
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#define AFE_ENPADIO_OFFSET 0x00000014
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#define AFE_BGREG_OFFSET 0x00000018
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#define AFE_ACCESSAR_ID_OFFSET 0x00000400
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#define AFE_PDADC_OFFSET 0x00000404
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#define AFE_PDSARH_OFFSET 0x00000408
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#define AFE_PDSARL_OFFSET 0x0000040C
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#define AFE_PDADCRFH_OFFSET 0x00000410
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#define AFE_PDADCRFL_OFFSET 0x00000414
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#define AFE_ACCTST_OFFSET 0x00000418
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#define AFE_ADCGN_OFFSET 0x0000041C
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#define AFE_ICTRL_OFFSET 0x00000420
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#define AFE_ICTLSTG_OFFSET 0x00000424
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#define AFE_RCTRLSTG_OFFSET 0x00000428
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#define AFE_TCTRLSTG_OFFSET 0x0000042c
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#define AFE_REFMOD_OFFSET 0x00000430
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#define AFE_REFTRIML_OFFSET 0x00000434
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#define AFE_REFTRIMH_OFFSET 0x00000438
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#define AFE_ADCR_OFFSET 0x0000043c
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#define AFE_DUMMY0_OFFSET 0x00000440
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#define AFE_DUMMY1_OFFSET 0x00000444
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#define AFE_DUMMY2_OFFSET 0x00000448
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#define AFE_DACAMP_OFFSET 0x0000044c
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#define AFE_CLMPTST_OFFSET 0x00000450
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#define AFE_CLMPDAT_OFFSET 0x00000454
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#define AFE_CLMPAMP_OFFSET 0x00000458
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#define AFE_CLAMP_OFFSET 0x0000045c
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#define AFE_INPBUF_OFFSET 0x00000460
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#define AFE_INPFLT_OFFSET 0x00000464
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#define AFE_ADCDGN_OFFSET 0x00000468
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#define AFE_OFFDRV_OFFSET 0x0000046c
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#define AFE_INPCONFIG_OFFSET 0x00000470
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#define AFE_PROGDELAY_OFFSET 0x00000474
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#define AFE_ADCOMT_OFFSET 0x00000478
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#define AFE_ALGDELAY_OFFSET 0x0000047c
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#define AFE_ACC_ID_OFFSET 0x00000800
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#define AFE_ACCSTA_OFFSET 0x00000804
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#define AFE_ACCNOSLI_OFFSET 0x00000808
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#define AFE_ACCCALCON_OFFSET 0x0000080c
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#define AFE_BWEWRICTRL_OFFSET 0x00000810
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#define AFE_SELSLI_OFFSET 0x00000814
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#define AFE_SELBYT_OFFSET 0x00000818
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#define AFE_REDVAL_OFFSET 0x00000820
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#define AFE_WRIBYT_OFFSET 0x00000824
|
||||
|
||||
/* AFE Register per module */
|
||||
#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET)
|
||||
#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET)
|
||||
#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET)
|
||||
#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET)
|
||||
#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET)
|
||||
#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET)
|
||||
#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET)
|
||||
#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET)
|
||||
#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET)
|
||||
#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET)
|
||||
#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET)
|
||||
#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET)
|
||||
#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET)
|
||||
#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET)
|
||||
#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET)
|
||||
#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET)
|
||||
#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET)
|
||||
#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET)
|
||||
#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET)
|
||||
#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET)
|
||||
#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET)
|
||||
#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET)
|
||||
#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET)
|
||||
#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET)
|
||||
#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET)
|
||||
#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET)
|
||||
#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET)
|
||||
#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET)
|
||||
#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET)
|
||||
#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET)
|
||||
#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET)
|
||||
#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET)
|
||||
#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET)
|
||||
#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET)
|
||||
#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET)
|
||||
#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET)
|
||||
#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET)
|
||||
#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET)
|
||||
#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET)
|
||||
#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET)
|
||||
#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET)
|
||||
#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET)
|
||||
#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET)
|
||||
#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET)
|
||||
#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET)
|
||||
#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET)
|
||||
#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET)
|
||||
#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET)
|
||||
|
||||
/* VDEC - Register offsets */
|
||||
#define VDEC_CFC1_OFFSET 0x00000000
|
||||
#define VDEC_CFC2_OFFSET 0x00000004
|
||||
#define VDEC_BRSTGT_OFFSET 0x00000024
|
||||
#define VDEC_HZPOS_OFFSET 0x00000040
|
||||
#define VDEC_VRTPOS_OFFSET 0x00000044
|
||||
#define VDEC_HVSHIFT_OFFSET 0x00000054
|
||||
#define VDEC_HSIGS_OFFSET 0x00000058
|
||||
#define VDEC_HSIGE_OFFSET 0x0000005C
|
||||
#define VDEC_VSCON1_OFFSET 0x00000060
|
||||
#define VDEC_VSCON2_OFFSET 0x00000064
|
||||
#define VDEC_YCDEL_OFFSET 0x0000006C
|
||||
#define VDEC_AFTCLP_OFFSET 0x00000070
|
||||
#define VDEC_DCOFF_OFFSET 0x00000078
|
||||
#define VDEC_CSID_OFFSET 0x00000084
|
||||
#define VDEC_CBGN_OFFSET 0x00000088
|
||||
#define VDEC_CRGN_OFFSET 0x0000008C
|
||||
#define VDEC_CNTR_OFFSET 0x00000090
|
||||
#define VDEC_BRT_OFFSET 0x00000094
|
||||
#define VDEC_HUE_OFFSET 0x00000098
|
||||
#define VDEC_CHBTH_OFFSET 0x0000009C
|
||||
#define VDEC_SHPIMP_OFFSET 0x000000A4
|
||||
#define VDEC_CHPLLIM_OFFSET 0x000000A8
|
||||
#define VDEC_VIDMOD_OFFSET 0x000000AC
|
||||
#define VDEC_VIDSTS_OFFSET 0x000000B0
|
||||
#define VDEC_NOISE_OFFSET 0x000000B4
|
||||
#define VDEC_STDDBG_OFFSET 0x000000B8
|
||||
#define VDEC_MANOVR_OFFSET 0x000000BC
|
||||
#define VDEC_VSSGTH_OFFSET 0x000000C8
|
||||
#define VDEC_DBGFBH_OFFSET 0x000000D0
|
||||
#define VDEC_DBGFBL_OFFSET 0x000000D4
|
||||
#define VDEC_HACTS_OFFSET 0x000000D8
|
||||
#define VDEC_HACTE_OFFSET 0x000000DC
|
||||
#define VDEC_VACTS_OFFSET 0x000000E0
|
||||
#define VDEC_VACTE_OFFSET 0x000000E4
|
||||
#define VDEC_HSTIP_OFFSET 0x000000EC
|
||||
#define VDEC_BLSCRY_OFFSET 0x000000F4
|
||||
#define VDEC_BLSCRCR_OFFSET 0x000000F8
|
||||
#define VDEC_BLSCRCB_OFFSET 0x000000FC
|
||||
#define VDEC_LMAGC2_OFFSET 0x00000104
|
||||
#define VDEC_CHAGC1_OFFSET 0x00000108
|
||||
#define VDEC_CHAGC2_OFFSET 0x0000010C
|
||||
#define VDEC_MINTH_OFFSET 0x00000114
|
||||
#define VDEC_VFRQOH_OFFSET 0x0000011C
|
||||
#define VDEC_VFRQOL_OFFSET 0x00000120
|
||||
#define VDEC_THSH1_OFFSET 0x00000124
|
||||
#define VDEC_THSH2_OFFSET 0x00000128
|
||||
#define VDEC_NCHTH_OFFSET 0x0000012C
|
||||
#define VDEC_TH1F_OFFSET 0x00000130
|
||||
|
||||
/* VDEC Register per module */
|
||||
#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET)
|
||||
#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET)
|
||||
#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET)
|
||||
#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET)
|
||||
#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET)
|
||||
#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET)
|
||||
#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET)
|
||||
#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET)
|
||||
#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET)
|
||||
#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET)
|
||||
#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET)
|
||||
#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET)
|
||||
#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET)
|
||||
#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET)
|
||||
#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET)
|
||||
#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET)
|
||||
#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET)
|
||||
#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET)
|
||||
#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET)
|
||||
#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET)
|
||||
#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET)
|
||||
#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET)
|
||||
#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET)
|
||||
#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET)
|
||||
#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET)
|
||||
#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET)
|
||||
#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET)
|
||||
#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET)
|
||||
#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET)
|
||||
#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET)
|
||||
#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET)
|
||||
#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET)
|
||||
#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET)
|
||||
#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET)
|
||||
#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET)
|
||||
#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET)
|
||||
#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET)
|
||||
#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET)
|
||||
#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET)
|
||||
#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET)
|
||||
#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET)
|
||||
#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET)
|
||||
#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET)
|
||||
#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET)
|
||||
#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET)
|
||||
#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET)
|
||||
#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET)
|
||||
#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET)
|
||||
|
||||
#define VDEC_VIDMOD_M625_SHIFT 4
|
||||
#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT)
|
||||
|
||||
#define VDEC_VIDMOD_PAL_SHIFT 7
|
||||
#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT)
|
||||
|
||||
struct sensor_data {
|
||||
u32 width;
|
||||
u32 height;
|
||||
u32 pixel_fmt;
|
||||
u32 std_id;
|
||||
};
|
||||
|
||||
void vadc_config(u32 vadc_in);
|
||||
void vadc_get_std(struct sensor_data *vadc);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue