dt-bindings: sunxi: Update clock/reset binding headers
Some devicetree updates make use of newly-exposed clocks and resets. To support that, copy the binding headers from the Linux v5.18-rc1 tag. Signed-off-by: Samuel Holland <samuel@sholland.org>
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					@ -113,7 +113,7 @@
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#define CLK_USB_OHCI0		91
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					#define CLK_USB_OHCI0		91
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#define CLK_USB_OHCI1		93
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					#define CLK_USB_OHCI1		93
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					#define CLK_DRAM		94
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#define CLK_DRAM_VE		95
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					#define CLK_DRAM_VE		95
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#define CLK_DRAM_CSI		96
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					#define CLK_DRAM_CSI		96
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#define CLK_DRAM_DEINTERLACE	97
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					#define CLK_DRAM_DEINTERLACE	97
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					@ -1,17 +1,8 @@
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					/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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					/*
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 * Copyright 2016 Maxime Ripard
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					 * Copyright 2016 Maxime Ripard
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 *
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					 *
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 * Maxime Ripard <maxime.ripard@free-electrons.com>
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					 * Maxime Ripard <maxime.ripard@free-electrons.com>
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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					 */
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#ifndef _DT_BINDINGS_CLK_SUN5I_H_
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					#ifndef _DT_BINDINGS_CLK_SUN5I_H_
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					@ -100,7 +91,7 @@
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#define CLK_AVS			96
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					#define CLK_AVS			96
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#define CLK_HDMI		97
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					#define CLK_HDMI		97
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#define CLK_GPU			98
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					#define CLK_GPU			98
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					#define CLK_MBUS		99
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#define CLK_IEP			100
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					#define CLK_IEP			100
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#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
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					#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
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					@ -49,6 +49,8 @@
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#define CLK_PLL_VIDEO1_2X	13
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					#define CLK_PLL_VIDEO1_2X	13
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					#define CLK_PLL_MIPI		15
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#define CLK_CPU			18
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					#define CLK_CPU			18
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#define CLK_AHB1_MIPIDSI	23
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					#define CLK_AHB1_MIPIDSI	23
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					@ -43,6 +43,8 @@
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#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
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					#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
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#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
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					#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
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					#define CLK_PLL_MIPI		13
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#define CLK_CPUX		18
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					#define CLK_CPUX		18
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#define CLK_BUS_MIPI_DSI	23
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					#define CLK_BUS_MIPI_DSI	23
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					@ -126,7 +126,7 @@
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#define CLK_USB_OHCI1		93
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					#define CLK_USB_OHCI1		93
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#define CLK_USB_OHCI2		94
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					#define CLK_USB_OHCI2		94
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#define CLK_USB_OHCI3		95
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					#define CLK_USB_OHCI3		95
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					#define CLK_DRAM		96
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#define CLK_DRAM_VE		97
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					#define CLK_DRAM_VE		97
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#define CLK_DRAM_CSI		98
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					#define CLK_DRAM_CSI		98
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#define CLK_DRAM_DEINTERLACE	99
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					#define CLK_DRAM_DEINTERLACE	99
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					@ -104,4 +104,8 @@
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#define CLK_MIPI_CSI		73
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					#define CLK_MIPI_CSI		73
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					/* Clocks not available on V3s */
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					#define CLK_BUS_I2S0		75
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					#define CLK_I2S0		76
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#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
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					#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
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					@ -1,17 +1,8 @@
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					/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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					/*
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 * Copyright 2016 Maxime Ripard
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					 * Copyright 2016 Maxime Ripard
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 *
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					 *
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 * Maxime Ripard <maxime.ripard@free-electrons.com>
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					 * Maxime Ripard <maxime.ripard@free-electrons.com>
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 *
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					 | 
				
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 * This program is free software; you can redistribute it and/or modify
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					 | 
				
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 * it under the terms of the GNU General Public License as published by
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					 | 
				
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 * the Free Software Foundation; either version 2 of the License, or
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					 | 
				
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 * (at your option) any later version.
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					 | 
				
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 *
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					 | 
				
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 * This program is distributed in the hope that it will be useful,
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					 | 
				
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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					 | 
				
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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					 | 
				
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 * GNU General Public License for more details.
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 */
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					 */
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#ifndef _RST_SUN5I_H_
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					#ifndef _RST_SUN5I_H_
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					@ -75,4 +75,7 @@
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#define RST_BUS_UART1		50
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					#define RST_BUS_UART1		50
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#define RST_BUS_UART2		51
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					#define RST_BUS_UART2		51
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					/* Reset lines not available on V3s */
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					#define RST_BUS_I2S0		52
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#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
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					#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
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